Bus Analysis in Allegro PCB SI

Cadence PCB Design Blogs http://www.mxbit.co.in What's Good About PCB SI Signal Integrity Bus Analysis? Allegro 16.5 Has a Few New Enhancements! Posted: 27 Mar 2012 06:51 AM PDT Address Bus Topology Support Part of the setup for Bus Analysis in Allegro PCB SI (for Cadence Online Support access click here) is to indicate the strobe or clock net that is to be associated with each bit of the bus being simulated. This process is straightforward for a data, bus but becomes more complicated for an address bus. This is illustrated in the diagram below:   In this example there are two strobe nets that control the DATA signals. They are DATA_STROBE0 and DATA_STROBE1 and each connects to two memory SDRAMs. Each bit of the DATA bus connects to a single SDRAM so it's easy to specify which strobe is to be used when simulating any given bit of the DATA bus. For example, when simulating DATA8, DATA_STROBE0 is to be used; when simulating DATA24, DATA_STROBE1 will be used. The ADDRESS bus is different in that each bit of this bus goes to every SDRAM. This bus is controlled by two clock signals, ADDRESS_CLOCK0 and ADDRESS_CLOCK1. This makes it more complicated to specify which clock is to be used for any given bit of the ADDRESS bus. For example, when simulating ADDRESS0 with SDRAM0 active, ADDRESS_CLOCK0 should be used but when simulating ADDRESS0 with SDRAM3 active, ADDRESS_CLOCK1 should be used. The 16.3 Bus Setup dialog form allows you to assign strobe or clock nets to each bit of the bus being simulated. This only allows a single strobe or clock to be assigned to any given bit of the bus. Once a bit has been assigned it is no longer available in the Unassigned Bus Xnets list. To solve this problem this form has been updated in 16.5 to optionally allow multiple bus Xnets to be assigned to the same clock or strobe signal. When a specific clock is selected, the Bus Xnets that have been assigned to another clock will no longer be removed from the Unassigned Bus Xnets list. This allows them to be assigned to multiple clocks/strobes. Using the example shown above, assume that the ADDRESS bus members are assigned to the ADDRESS_CLOCK nets. In this case you would first select ADDRESS_CLOCK0 and assign all of the ADDRESS nets to that clock. You would then select ADDRESS_CLOCK1 and again assign all of the ADDRESS nets to that clock. When a bit of the ADDRESS is simulated the software determines which of the two assigned clock nets to use based on the SDRAM that is being activated. The 16.3 bus analysis report produces all the raw data needed to determine timing closure for a source synchronous interface, but does not perform the needed calculations to arrive at a pass/fail timing test. In 16.5, the timing margin is now included in the bus analysis report. I look forward to your comments. Jerry "GenPart" Grzenia You are subscribed to email updates from Cadence PCB Design Blogs To stop receiving these emails, you may unsubscribe now. Email delivery powered by Google Google Inc., 20 West Kinzie, Chicago IL USA 60610