PCB Router Staggered Via Rules

Mxbit Cadence PCB Design Blogs What's Good About Allegro PCB Router Staggered Via Rules? See for yourself in 16.5! Posted: 06 Mar 2012 09:12 AM PST Just a quick blog today on a new 16.5 Allegro PCB Router enhancement for Staggered Via Rules. The stagger gap value is defined by rules at the following levels: PCB Layer Class Net Region   Option Descriptions: on - turns the rule on. off - turns the rule off (default) min_gap - controls the minimum distance between consecutive vias in the pattern. If min_gap is not specified, a proper samenet bbvia/microvia to samenet bbvia/microvia clearance rule in effect controls the distance. An assigned negative value means no restricted min distance between consecutive vias in the pattern max_gap - controls the maximum distance between consecutive vias in the pattern. If max_gap is not specified (or assigned a negative value) any restrictions exist on max distance between consecutive vias in the pattern. Examples: #define PCB level rule for staggered bbvias/microvias rule PCB (staggered_via on (min_gap 0.1) (max_gap 0.8)) #redefine rule for staggered bbvias/microvias at '3_LAYER' rule layer 3_LAYER (staggered_via on (min_gap 0.2) (max_gap 0.7)) #redefine rule for staggered bbvias/microvias of nets #from 'NET_CLASS1' class rule class NET_CLASS1 (staggered_via on (min_gap 0.3) (max_gap 0.6)) #disable PCB level rule (similar rules at different hierarchy #levels are left enabled) rule PCB (staggered_via off) COST of Via Stagger Violation: Cost descriptor values are interpreted by the PCB autorouter as follows: - Forbidden, wrong staggered bbvia patterns aren't allowable for building (default) - High, additional cost on wrong staggered bbvia patterns 100 - Medium, additional cost on wrong staggered bbvia patterns 25 - Low, additional cost on wrong staggered bbvia patterns 8 - Free, no additional cost on wrong staggered bbvia patterns Note: At the "converge" stage (either after 5th routing iteration or during "filter" command execution) the autorouter resets this cost to the forbidden value automatically. I look forward to your input on this capability. Jerry "GenPart" Grzenia What's Good About Allegro DFM/DRC Updates? 16.5 Has a Few New Enhancements! Posted: 28 Feb 2012 08:00 AM PST Allegro PCB Editor has been enhanced in the 16.5 release with three (3) additional DRC checks and an enhanced DFA utility for a 4th DRC entry, and now allows backdrilling from any layer. Read on for all the details … Max Neck Length DRC Presently, the Max Neck Length constraint is applied on a per-segment basis for CLINEs in a routed design; each segment is measured independently within a necked section and compared to the constraint value. As long as each individual segment is less than the max length, no violation is deemed to exist. For CLINE necks that span more than a single segment, each individual segment may be shorter than the length constraint while the total length of the necked section may exceed the constrained length without report of violation. In 16.5, the behavior of the Max Neck Length DRC is changed to constrain the cumulative length of necked sections to not exceed the prescribed Max Neck Length value. This is a behavioral change and there is no way to use the old methodology. Duplicate Drill hole DRC check Redundant drill hole checks are deemed to be an important resource for users interested in incorporation of design for fabrication (DFF) methodologies early in the product design process. Redundant drill holes can be created inadvertently through operations such as design element copy (import subdrawing). Unnecessary and potentially damaging fabrication steps can be eliminated by flagging drill hole redundancies. New Design level check detects duplicate drill holes spanning the same layers and are based on the following: •    Duplicate drill holes may be based on the same or different pad stack definitions. •    Simple overlaps (non-identical drill locations) are excluded from this definition. •    Drill holes must share all the same layers to be considered duplicate. This check is set in the Design Mode UI and the DRC identifier is DH: Minimum Metal to Metal Clearance DRC The New Design level check ensures minimum metal to metal clearance is met. This check aligns Allegro PCB Editor closely with CAD/CAM tools as well as checking occurrences of spacing errors as a result of certain spacing modes being accidentally set to OFF. This check may be best served running near design completion as it will produce redundant DRCs in most cases assuming your entire spacing suite of modes is set to ON. This is set in the Design Options folder. You must also enable the DRC check in the Design Modes UI: Net Short Report Net shorts are currently reported as spacing DRCs with a value of 0. It can be difficult to discern spacing issues (air gap) from actual shorts. Designers tend to view shorts as the higher priority item to address. A new "traffic light" has been added to the Status form and a new report can be executed to display nets which are shorted: DFA Enhancement The DFA spreadsheet now supports a 4th DRC entry to accommodate requests for separate values for Side to End and End to Side. In the example below, both represent a "Side to End" condition where different values need to be applied: DFA Table Updates •    DRC syntax enhanced to support 4th entry. (End to Side) •    The symbol considered the "Reference Symbol" is located in the "column". •    If "End to Side" value is not present, the DRC uses the "Side to End" value for both conditions. •    When comparing two identical symbols, only the "Side to End" value is used. End to Side is considered superfluous. •    When down-revving the database to 16.3, the Side to End value is ignored by the DRC system.   Backdrill (Any Layer) Backdrilling was introduced in the 15.7 release. Since its introduction there have been various enhancement requests related to extra clearance requirements and back off distance to the target layer. For 16.5, backdrilling capability in Allegro is enhanced to allow any layer to any layer configurations. Currently backdrilling is restricted to starting from the top or bottom layer. Due to board composite construction techniques used with some HDI and sub-laminate designs this need has become more critical. 16.3 example: 16.5 example: I look forward to your input about these new capabilities. Jerry "GenPart" Grzenia Email delivery powered by Google