Bus Analysis in Allegro PCB SI

Cadence PCB Design Blogs http://www.mxbit.co.in What's Good About PCB SI Signal Integrity Bus Analysis? Allegro 16.5 Has a Few New Enhancements! Posted: 27 Mar 2012 06:51 AM PDT Address Bus Topology Support Part of the setup for Bus Analysis in Allegro PCB SI (for Cadence Online Support access click here) is to indicate the strobe or clock net that is to be associated with each bit of the bus being simulated. This process is straightforward for a data, bus but becomes more complicated for an address bus. This is illustrated in the diagram below:   In this example there are two strobe nets that control the DATA signals. They are DATA_STROBE0 and DATA_STROBE1 and each connects to two memory SDRAMs. Each bit of the DATA bus connects to a single SDRAM so it's easy to specify which strobe is to be used when simulating any given bit of the DATA bus. For example, when simulating DATA8, DATA_STROBE0 is to be used; when simulating DATA24, DATA_STROBE1 will be used. The ADDRESS bus is different in that each bit of this bus goes to every SDRAM. This bus is controlled by two clock signals, ADDRESS_CLOCK0 and ADDRESS_CLOCK1. This makes it more complicated to specify which clock is to be used for any given bit of the ADDRESS bus. For example, when simulating ADDRESS0 with SDRAM0 active, ADDRESS_CLOCK0 should be used but when simulating ADDRESS0 with SDRAM3 active, ADDRESS_CLOCK1 should be used. The 16.3 Bus Setup dialog form allows you to assign strobe or clock nets to each bit of the bus being simulated. This only allows a single strobe or clock to be assigned to any given bit of the bus. Once a bit has been assigned it is no longer available in the Unassigned Bus Xnets list. To solve this problem this form has been updated in 16.5 to optionally allow multiple bus Xnets to be assigned to the same clock or strobe signal. When a specific clock is selected, the Bus Xnets that have been assigned to another clock will no longer be removed from the Unassigned Bus Xnets list. This allows them to be assigned to multiple clocks/strobes. Using the example shown above, assume that the ADDRESS bus members are assigned to the ADDRESS_CLOCK nets. In this case you would first select ADDRESS_CLOCK0 and assign all of the ADDRESS nets to that clock. You would then select ADDRESS_CLOCK1 and again assign all of the ADDRESS nets to that clock. When a bit of the ADDRESS is simulated the software determines which of the two assigned clock nets to use based on the SDRAM that is being activated. The 16.3 bus analysis report produces all the raw data needed to determine timing closure for a source synchronous interface, but does not perform the needed calculations to arrive at a pass/fail timing test. In 16.5, the timing margin is now included in the bus analysis report. I look forward to your comments. Jerry "GenPart" Grzenia You are subscribed to email updates from Cadence PCB Design Blogs To stop receiving these emails, you may unsubscribe now. Email delivery powered by Google Google Inc., 20 West Kinzie, Chicago IL USA 60610

APD's Symbol Editor App Mode

Mxbit Cadence PCB Design Blogs What's Good About APD's Symbol Editor App Mode? You'll Need the 16.5 Release to See! Posted: 20 Mar 2012 10:03 AM PDT In an IC package design, it is common for the designer to customize the BGA component, or even the die components (if they are still subject to changes by the IC owner) in order to optimize the package substrate for cost and efficiency. In order to do this, changes to the components and physical symbols representing them in the substrate layout are often necessary. Since the 14.2 release, Cadence IC Packaging physical layout tools like APD and Cadence SiP Layout have provided context-based editing commands for making changes to the BGA and die symbols directly within the package substrate design (instead of modifying the library symbols via the symbol (.dra) editor, as would be done for a PCB design). With the release of 16.5 Allegro Package Designer, these aging BGA and die editor commands are being phased out and replaced with the Symbol Editor application mode. As a package designer, this new application mode environment gives you all the same power of those old commands – and more! – in an intuitive environment specifically geared towards productive editing of your components. Want to know more details? Read on! It might be best to watch a video of this feature  (available on Cadence Online Support – COS) before reading the exhaustive information below. IC package designers normally consider the package BGA component as a part of the package design and therefore changeable.  In addition, the IC design team may be developing one or more of the dies within the package or SiP concurrently with the package, and thus the package designer may be able to suggest die changes.  This means that the package designer may need to be able to add, remove, rename, or move pins and even change the body size of die and BGA components during package layout.  As system designs become even more complex and dense, customers are becoming increasingly dependent on system-level floor planning, partitioning and concurrent design.  As a result, PCB/Package co-design is developing as a vital requirement for systems customers.  Gone are the large forms that hide areas of your canvas window, the frequent cursor movements between the canvas and the forms themselves, the lack of show element support while editing a symbol, and the inability to run other features and make efficient design trade-offs. Replacing this is a context-sensitive environment where you can move naturally between modifying pins to updating escape routing and bond finger placement; an application mode that reacts to what you are working on, and works to make your life easier. It stays out of the way until it is needed, and fades into the background once you are done with it. This change may seem like a dramatic design flow impact, but it is really not. The user will still be performing the same edits that they do today, but the manner in which they do them will be much faster and more intuitive. It will also better align with the current use model of the rest of the tool. The following are some key features of the new 16.5 APD and SiP capabilities. • You can move seamlessly between editing the symbol and the package substrate. You can move a pin to eliminate a wire-wire DRC at the die side, then move immediately into updating the wire bond pattern to compensate. Or, you could be changing a BGA ball padstack to get more routes through a channel, then go and change the via structure that connects to the ball and update the pin escape. Here is an example of how a pin was deleted in 16.3: Here is a screenshot of deleting a pin in 16.5 (using the PCB Editor): Here is a screenshot of deleting a pin in 16.5 (using the Symbol App mode): • Full-context editing: You can see the current routing, all the other components in the substrate, etc. all while making edits to the components as necessary. No need to look at separate windows, get in/out of a different command environment, etc. Use show element, highlighting, net coloring, data tips, etc. to get the info you need to make the most intelligent design decisions quickly and efficiently.  Here is an example of a pin being added to the BGA ball pattern in 16.3: Here is an example of how this is done in 16.5: • Multi-instance editing. Because the app mode modifies the symbol/component definitions, if you have 4 instances of a die in your design, as an example, adding a pin on one instance through the app mode instantly updates all three other instances with those same changes. The "stretch etch" settings are applied across all instances, as well. So, if each instance of the die had a slightly different fanout pattern, that is compensated for as a pin is moved, deleted, swapped, etc. at each instance level.  • Editing of additional component types. Previously, you could only edit dies and BGAs. Now, if your design flow permits, you can edit any component type by this method --  Modify your plating bar, make changes to that discrete, etc. all from the comfort of that one environment:: • No big, bulky forms taking up screen real estate. The BGA and Die editors had a massive form that you had to use to control everything. Now, all the things you can do in the app mode have been simplified to the point where their settings fit in the options tab of the main window, leaving the full canvas available and visible at all times.  • "Instant on" editing. With the older editors, you had to start the command, pick the component to edit, enter the command, make changes, and then get back out. Depending on the complexity of the component and the level of completeness of the substrate routing, this could take quite some time just to get in/out. Now, there is none of that. • Context-sensitive RMB menus. This is like all other app modes. There's no switching between different states or tabs of forms or anything like that. RMB on a pin or set of pins and pick move. The pins show up on your cursor and you can move them around. You can even customize what operations are performed when you do a double-click or a click-and-drag of an object. So, you don't have to do anything to move a pin beyond dragging it to where you want it to go I look forward to your feedback on this new 16.5 capability! Jerry "GenPart" Grzenia You are subscribed to email updates from Cadence PCB Design Blogs To stop receiving these emails, you may unsubscribe now. Email delivery powered by Google Google Inc., 20 West Kinzie, Chicago IL USA 60610 www.mxbit.co.in

APD's Die Abstract Libraries

Mxbit Cadence PCB Design Blogs What's Good About APD's Die Abstract Libraries? You'll Need the 16.5 Release to See! Posted: 24 Jan 2012 10:00 AM PST In System in Package (SiP) 16.3, the co-design die flow introduced the distributed co-design flow concept, where there is no direct interaction with I/O Planner. Die information flowing between Encounter and SiP Layout is done via a die abstract.  In flows up through 16.3, you first need to load the LEF files for the cell library used by the IC design into the LEF Library Manager and create the Condensed Macro Library (CML) files.  The CML files would need to be updated anytime the LEF files changed.  In the flow for Allegro Package Designer (APD) 16.5, Encounter will generate die abstracts including information for all layers for each pin of each I/O cell macro that is used in the die.  The intent of the 16.3 distributed co-design flow using the die abstract was to provide the necessary library information inside the die abstract to allow us to eliminate the use of LEF/CML files in the co-design flow.  However, there was no mechanism provided in that flow for the user to identify the die pins and connection pins, so LEF files were still needed.  In 16.5 we support the distributed co-design flow allowing the user to choose to continue to load LEF/CML, create CML based on die abstract file, or not create CML at all. Not requiring creation of CML files would be the default mechanism. Read on for more details … Flow Impact The intent of this feature is to provide IC library manager capabilities needed to support a new distributed co-design flow option.  The only difference from a current distributed co-design flow is that by default no additional library information other than provided in die abstract file is needed, and no IC Library Manager user interface options are needed. If the user chooses, they can also either create a CML file based on die abstract file, which again is a new capability, or use the same 16.3 based flow of creating a CML file based on LEF library. Use Models: Add Co-design Die from Die Abstract file (simple mode without IC Library Manager UI) •        The Add Co-design Die command is invoked. •        The New Design from Die Abstract file tab is selected. •        User enters or browses to point to a Die Abstract file. •        The design name (read from the Die Abstract file, and becomes the component name) appears on the form. •        User presses OK button to add the die to the drawing, or Cancel to abort command. •       The die placement form appears, an image of the die appears on the cursor and the user can place the die into the SiP design. Add Co-design Die from Die Abstract file (cml file to be created based on Die Abstract file) •        The Add Co-design Die command is invoked. •        The New Design from Die Abstract file tab is selected. •        User enters or browses to point to a Die Abstract file. •       Press Library Manager Button to invoke IC Library Manager. •       By default the same Die Abstract file will be selected in the IC Library Manager, as the file was just browsed to. •       User selects options to use for IC library processing, and cml file is created. The name of the file is the same as die abstract file name with .cml extension. The Auto create button needs to be pressed in order to create the .cml file and attach it to the database. The Auto-create button will be disabled until the user has actually opened the Options form and pressed OK.  •       If CML file is created by mistake, press Remove CML button to remove CML file. By removing it and not creating another CML, or going to LEF option, user is back to default behavior. •        The design name (read from the Die Abstract file, and becomes the component name) appears on the form. •        User presses OK button to add the die to the drawing, or Cancel to abort command. •       The die placement form appears, an image of the die appears on the cursor and the user can place the die into the SiP design. Add Co-design Die from Die Abstract file (cml files to be created based on  .ldf file, this is the 16.3 flow) •        The Add Co-design Die command is invoked. •        The New Design from Die Abstract file tab is selected. •        User enters or browses to point to a Die Abstract file. •       Press Library Manager Button to invoke IC Library Manager. •       By default the same Die Abstract file will be selected in the IC Library Manager, as the file was just browsed to. Select option .ldf file. Browse to ldf file. •       Use IC Library Manager the same way as it was used prior to 16.5. Exit library manager. •        The design name (read from the Die Abstract file, and becomes the component name) appears on the form. •        User presses OK button to add the die to the drawing, or Cancel to abort command. •       The die placement form appears, an image of the die appears on the cursor and the user can place the die into the SiP design. Update Co-design Die from Die Abstract File •       The user must first invoke the Die Editor command. •       When the Die Editor launches on the Component Selection form if a co-design component with Die Abstract co-design source is selected, a type in field or browse button can be used to select the new Die Abstract file from disk. If new file is not selected by default the method that was used previously to add or update the die will be used. If new die abstract file is selected, default would be to use simple case, as described above in Add Co-design. If user chooses to use IC Library Manager, press Library Manager Button. •       Note that updating a co-design die from a new Die Abstract file will replace the existing die layout with exactly what is in the Die Abstract file.  Thus any changes that were made to the die in SiP Layout, but not incorporated in the new Die Abstract file imported to update the die will be lost.  Also note that the abstract is not incremental, and must include complete information about the die. •       Offer options to compare the new Die Abstract only, without updating the die, update the die only without reporting changes, or update the die and report changes via Component Compare report.  The default is to update the die from the Die Abstract file without reporting changes. •       The form will include a note to the user informing him that updating the die from the Die Abstract file will replace the die layout with what is in the file, even if changes have been made to the die in SiP Layout that are not included in the Die Abstract file. Menu and Command Line Access The access to these commands is the same as in previous releases. The Add functionality can be launched by typing "add co-design die" in the command-line window, or through the "Add Co-design Die…" option of the Add menu.  The Die Editor is invoked by typing "die editor" in the command-line window, or through the "Die" option of the "Edit" menu. On the add co-design form and on update die "Library Manager" button will be available, which will invoke IC Library Manager. To invoke ICLM from command line, "lef lib" should be typed (the same as in 16.3) or "ic lib" will also invoke library manager. Note that the IC Library Manager in LEF library only mode is still available via the menu and command line.  It will remain exactly the same as it was in 16.3. Graphical User Interface Add Co-design Die As mentioned before, the default behavior for the add co-design die from Die Abstract would be adding library information stored in the Die Abstract itself without using IC Library Manager. There is no visual difference to the form for the add co-design die. The main difference is in when OK button becomes enabled: The OK Button allows the adding of the die to proceed. This button is grayed out (disabled) until the following conditions are true -- a) The Die Abstract file has been read successfully; b) there is a valid Design Name present; c) the die component does not already exist. In prior releases OK button was disabled until the LEF Library manager has been configured with an appropriate LDF file and Library. This is no longer the case. By default, the Library information used is the information stored directly in Die Abstract file.  The methodology used to determine die pins and RDL connection points. As in the prior releases Library Manager Button is available to allow user to configure the IC Library Manager, if the user chooses to do so. Die Editor Capability to Update Die from New Die Abstract If you invoke the Die Editor command and select a co-design die to edit that has a Die Abstract file as its co-design source, the Die Editor Component Selection form appears as in Figure 1.  This form shows that the co-design source is a Die Abstract file currently stored in the database.  There is also a file browse button, with label (…), to select a new Die Abstract file from disk that contains an ECO from the IC tools.  Selecting a new file in this way will update the die from that new Die Abstract file. This is all the same as it was in 16.3.  New for 16.5 is that a Library Manager Button has been added to allow users to select the way they want to use library information: The Die Editor Component Selection form shows the Co-Design Source as Die Abstract, with a browser button to select a new die abstract to use to update the die from an IC ECO, and Library Manager Button to allow user to configure IC Library Manager. Co-Design Source Die Abstract – Type in field that by default shows the current Die Abstract file is the <Current in Database>.  This is a typable field where you can type in the name of a new Die Abstract file containing an ECO from the IC tool, which would then be used to update the die before launching the Die Editor.  If you keep the default, <Current in Database>, when the Die Editor is launched after pressing the Next button, it loads the I/O driver cell information from the existing Die Abstract file contained in the database, rather than allowing update from a new Die Abstract.  This is the same as in 16.3. … button – Opens a file browser to allow the user to browse for a new Die Abstract file, containing an ECO from the IC tool, from which to update the co-design die. Library Manager button - Allows user to configure the IC Library Manager. When the Next button is subsequently pressed, the ECO Die Abstract file will be read and the die updated from it before launching the Die Editor. IC Library Manager (iclm) Other than the new radio button at the top, when LEF Library is chosen, the rest of the fields on the form behave exactly as in 16.3. The Library settings section, including the LEF files list, of the form will be disabled when the Die Abstract option is chosen.  Only the CML settings section will be enabled. Browse… button – Opens a file browser to allow the user to browse for a new Die Abstract file, containing an ECO from the IC tool, from which to update the co-design die.  Once a new die abstract is selected like this, it will be passed back to the Edit Die form to update that form so the newly selected file will be read to replace the previous version of the die. The CML settings behave exactly the same when the Die Abstract option is chosen as they did in 16.3 (and when the LEF Library option is chosen).  The only difference is that only a single .cml file will be created, and it will be retained within the .sip database for future use when processing the die abstract. Remove button  -- Visible and active only if CML file is created and attached to the database. Press the button to remove CML as database attachment. By doing so, the library manager will process the die abstract using default algorithm. If using LEF/CML files option is the choice, select LEF Library radio button. Please share your findings with this capability. Jerry "GenPart" Grzenia You are subscribed to email updates from Cadence PCB Design Blogs To stop receiving these emails, you may unsubscribe now. Email delivery powered by Google Google Inc., 20 West Kinzie, Chicago IL USA 60610

PCB Router Staggered Via Rules

Mxbit Cadence PCB Design Blogs What's Good About Allegro PCB Router Staggered Via Rules? See for yourself in 16.5! Posted: 06 Mar 2012 09:12 AM PST Just a quick blog today on a new 16.5 Allegro PCB Router enhancement for Staggered Via Rules. The stagger gap value is defined by rules at the following levels: PCB Layer Class Net Region   Option Descriptions: on - turns the rule on. off - turns the rule off (default) min_gap - controls the minimum distance between consecutive vias in the pattern. If min_gap is not specified, a proper samenet bbvia/microvia to samenet bbvia/microvia clearance rule in effect controls the distance. An assigned negative value means no restricted min distance between consecutive vias in the pattern max_gap - controls the maximum distance between consecutive vias in the pattern. If max_gap is not specified (or assigned a negative value) any restrictions exist on max distance between consecutive vias in the pattern. Examples: #define PCB level rule for staggered bbvias/microvias rule PCB (staggered_via on (min_gap 0.1) (max_gap 0.8)) #redefine rule for staggered bbvias/microvias at '3_LAYER' rule layer 3_LAYER (staggered_via on (min_gap 0.2) (max_gap 0.7)) #redefine rule for staggered bbvias/microvias of nets #from 'NET_CLASS1' class rule class NET_CLASS1 (staggered_via on (min_gap 0.3) (max_gap 0.6)) #disable PCB level rule (similar rules at different hierarchy #levels are left enabled) rule PCB (staggered_via off) COST of Via Stagger Violation: Cost descriptor values are interpreted by the PCB autorouter as follows: - Forbidden, wrong staggered bbvia patterns aren't allowable for building (default) - High, additional cost on wrong staggered bbvia patterns 100 - Medium, additional cost on wrong staggered bbvia patterns 25 - Low, additional cost on wrong staggered bbvia patterns 8 - Free, no additional cost on wrong staggered bbvia patterns Note: At the "converge" stage (either after 5th routing iteration or during "filter" command execution) the autorouter resets this cost to the forbidden value automatically. I look forward to your input on this capability. Jerry "GenPart" Grzenia What's Good About Allegro DFM/DRC Updates? 16.5 Has a Few New Enhancements! Posted: 28 Feb 2012 08:00 AM PST Allegro PCB Editor has been enhanced in the 16.5 release with three (3) additional DRC checks and an enhanced DFA utility for a 4th DRC entry, and now allows backdrilling from any layer. Read on for all the details … Max Neck Length DRC Presently, the Max Neck Length constraint is applied on a per-segment basis for CLINEs in a routed design; each segment is measured independently within a necked section and compared to the constraint value. As long as each individual segment is less than the max length, no violation is deemed to exist. For CLINE necks that span more than a single segment, each individual segment may be shorter than the length constraint while the total length of the necked section may exceed the constrained length without report of violation. In 16.5, the behavior of the Max Neck Length DRC is changed to constrain the cumulative length of necked sections to not exceed the prescribed Max Neck Length value. This is a behavioral change and there is no way to use the old methodology. Duplicate Drill hole DRC check Redundant drill hole checks are deemed to be an important resource for users interested in incorporation of design for fabrication (DFF) methodologies early in the product design process. Redundant drill holes can be created inadvertently through operations such as design element copy (import subdrawing). Unnecessary and potentially damaging fabrication steps can be eliminated by flagging drill hole redundancies. New Design level check detects duplicate drill holes spanning the same layers and are based on the following: •    Duplicate drill holes may be based on the same or different pad stack definitions. •    Simple overlaps (non-identical drill locations) are excluded from this definition. •    Drill holes must share all the same layers to be considered duplicate. This check is set in the Design Mode UI and the DRC identifier is DH: Minimum Metal to Metal Clearance DRC The New Design level check ensures minimum metal to metal clearance is met. This check aligns Allegro PCB Editor closely with CAD/CAM tools as well as checking occurrences of spacing errors as a result of certain spacing modes being accidentally set to OFF. This check may be best served running near design completion as it will produce redundant DRCs in most cases assuming your entire spacing suite of modes is set to ON. This is set in the Design Options folder. You must also enable the DRC check in the Design Modes UI: Net Short Report Net shorts are currently reported as spacing DRCs with a value of 0. It can be difficult to discern spacing issues (air gap) from actual shorts. Designers tend to view shorts as the higher priority item to address. A new "traffic light" has been added to the Status form and a new report can be executed to display nets which are shorted: DFA Enhancement The DFA spreadsheet now supports a 4th DRC entry to accommodate requests for separate values for Side to End and End to Side. In the example below, both represent a "Side to End" condition where different values need to be applied: DFA Table Updates •    DRC syntax enhanced to support 4th entry. (End to Side) •    The symbol considered the "Reference Symbol" is located in the "column". •    If "End to Side" value is not present, the DRC uses the "Side to End" value for both conditions. •    When comparing two identical symbols, only the "Side to End" value is used. End to Side is considered superfluous. •    When down-revving the database to 16.3, the Side to End value is ignored by the DRC system.   Backdrill (Any Layer) Backdrilling was introduced in the 15.7 release. Since its introduction there have been various enhancement requests related to extra clearance requirements and back off distance to the target layer. For 16.5, backdrilling capability in Allegro is enhanced to allow any layer to any layer configurations. Currently backdrilling is restricted to starting from the top or bottom layer. Due to board composite construction techniques used with some HDI and sub-laminate designs this need has become more critical. 16.3 example: 16.5 example: I look forward to your input about these new capabilities. Jerry "GenPart" Grzenia Email delivery powered by Google

Signal Integrity Application

Cadence PCB Design Blogs What's Good About PCB SI Signal Integrity Application Mode? It's in the 16.5 Release! Posted: 31 Jan 2012 08:00 AM PST In release 16.0, the concept of Application Modes was introduced. These application modes are used to set up the tool for specific tasks. The existing applications are General Edit, Etch Edit, and Placement. In 16.5, the Signal Integrity (SI) application mode has been added to be used for high-speed related tasks. An Application Mode is a "super command" telling Allegro the general function area the user will be working in, and includes the following related functionality: •    Highlighting objects on hover •    Context sensitive RMB menus •    Auto-execution of default commands on double-click or drag of an object •    A limited Find Filter Read on for more details … There are six different methods for accessing App Modes. One is through the User Preferences Editor (Setup > User Preferences). This sets the App Mode to start when an Allegro editor opens: The other five are all accessible from within the canvas and impact the current session: The SI application mode behaves in a manner similar to other application modes, but is only available when an SI license is available while in Allegro PCB Editor. If you are currently using Allegro PCB GXL and then select the SI app mode, the tool will stay in the same editor and the SI license will be checked out only when an SI feature is used. This feature is defined mostly in context sensitive menus in order to perform SI specific tasks but can also be seen in different datatips content by default and double click command on certain objects. The following picture shows the Right Mouse Menu in SI application mode when invoked from the empty canvas: Quick Utilities The Quick Utilities sub-menu is shown below: Context Sensitive Menus In the SI Application mode, when you right click on an object, the content of the menu is adapted to the object and what you most likely want to do. The following context sensitive menu are displayed on the right mouse button (RMB) menu for the listed objects:           Automatic execution of commands In addition to the context right mouse button menu, the application mode sets up commands that are automatically executed on certain objects (actions are with the left mouse button): The three items in bold italics under the Double-Click column are unique to the SI App mode. The rest overlap with other App Modes. Please share your experience with this new capability. Jerry "GenPart" Grzenia You are subscribed to email updates from Cadence PCB Design Blogs To stop receiving these emails, you may unsubscribe now. Email delivery powered by Google Google Inc., 20 West K mxbit.co.in

Allegro PCB SI 28 Gbps

Cadence PCB Design Blogs Altera 28 Gbps Stratix V IBIS-AMI Models Now Blazing Channels with Allegro PCB SI Posted: 24 Feb 2012 09:54 AM PST Altera and Cadence recently collaborated and completed correlation work with Allegro PCB SI using IBIS-AMI models for the Altera Stratix® V FPGAs.  Customers may now contact Altera and request IBIS-AMI models for the Stratix V that support all data rates from 600 Mbps to 28 Gbps.   The state of the art transceivers used in the Altera Stratix V support leading edge backplane protocols that run up to 12.5 Gbps, as well as the emerging standards for optical interfaces that are planned to be specified at up to 28 Gbps. Cadence went through a rigorous correlation study and was able to show accurate simulation results.  Altera now has the IBIS-AMI model kit for Allegro PCB SI ready to deliver to users of Cadence multi-gigabit signal integrity technology.  The kit includes the IBIS-AMI model for the TX driver with pre-emphasis and slew rate control as well as the RX input buffer with linear equalization, adaptive dispersion compensation engine (ADCE) and clock and data recovery (CDR). The integrated design and analysis solution from Cadence allows for channels to be designed for backplanes or large PCBs, and simulated on the fly with no need for translation from the design environment to a special simulation tool.  The Cadence Allegro PCB SI solution with the multi-gigabit option supports having the Altera Stratix V IBIS-AMI model pre-assigned to the transceiver pins on the PCB design, making it simple and easy to begin simulating the channels with millions of bits.  Changes to the channel can either be made on the PCB design canvas or in a topology exploration tool, Signal Explorer, which allows what-if changes to be incorporated into simulation without modifying the actual design.  "The integration of design and analysis made Cadence's Allegro PCB SI environment a natural fit for our state-of-the-art IBIS-AMI models for Stratix V FPGA transceivers," said Salman Jiva, product marketing manager for Altera's high-speed serial transceiver and signal integrity solutions.  "The correlation results we see insure our joint customers will get accurate results when using our models in the Allegro PCB SI environment."                                                     Click here to learn more about Allegro PCB SI.  Contact your local Altera Field representative to request IBIS-AMI Stratix V models from Altera in an Allegro PCB SI design-in kit. TeamAllegro This posting includes an audio/video/photo media file: Download Now You are subscribed to email updates from Cadence PCB Design Blogs To stop receiving these emails, you may unsubscribe now. Email delivery powered by Google Google Inc., 20 West Kinzie, Chicago IL USA 60610 mxbit