Friday, August 31, 2012

Allegro PCB Router Routing Changes

Cadence PCB Design Blogs

Cadence PCB Design Blogs



What's Good About Allegro PCB Router Routing Changes? 16.5 Has a Few New Enhancements!

Posted: 15 Aug 2012 08:00 AM PDT

The 16.5 Allegro PCB Router has a couple new improvements I'll cover today – Embedded Components Support and Route Quality Improvements.

Read on for more details …


Embedded Components Support

This functionality is basically transparent to the Allegro flow designer. The Router will just translate and route these components normally. For standalone users of the Allegro PCB Router, a new syntax has been added to support via keepouts that are required by embedded components for proper routing. For standalone users, changes have been made to add keepouts needed for embedded components.

Routing:

Proper fanouts should be completed before using the Router to ensure access to other layers. The fanouts for embedded components can go up or down as parts are no longer top/bottom mounted. If embedded devices are placed on plane layers, the router can't access pins on these layers. Also, the Allegro PCB Router can't terminate a via on a plane layer ,so fanout routines cannot do via-in-pad at these locations. So, the recommendation is to NOT place embedded components on plane layers.

Route Quality improvements

The Allegro PCB Router has focused on the quality of differential pair routing in particular.

Differential pair routing:

The routing engine has been enhanced to consider differential pair objects as a single entity and avoid the splitting of the differential pair. This will especially help when the differential pair is entering a regular pin array or BGA.

New Cost has been added to control the differential pair routing. This will allow designers to control the routing of differential pair when the differential pairs may split:

    cost dp_push_squeeze [free|forbidden|[0-100]]

[free]    Diffpair can be squeezed to produce uncouple violation (actual gap < gap-tolerance-) if required to produce DRC-free layout. actual gap < min_line_spacing is not allowed, and push is considered as failed.

[forbidden] Diffpair after push should maintain exact primary/neck gap; any squeeze is illegal.

However, Setting the value to forbidden may increase delay failures.

Post Routing Diff Pair Clean up improvements:

Enhancements have been made in post route geometry clean up for differential pairs. The improvements include, but are not limited to cleaning up staired patterns, removing bends, cleaning uncouple bumps and reliability improvements.
This further enhances the router's ability to provide good diff pair solutions. There are no additional controls or commands needed for these improvements. The "Clean" and "Critic" commands have been enhanced to incorporate these changes.

Please share your experiences using these new 16.5 capabilities.

Jerry "GenPart" Grzenia

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