Friday, August 31, 2012

PCB SI Adaptive Mesh Generation

Cadence PCB Design Blogs

Cadence PCB Design Blogs



What's Good About PCB SI Adaptive Mesh Generation? 16.5 Has Many New Enhancements!

Posted: 28 Aug 2012 08:00 AM PDT

The 16.5 PCB SI product's rectangular mesh scheme is used for shapes, cutouts, slots, anti-pads and voids within shapes. The mesh cell size you pre-specify is the maximum cell size ,and the system will automatically adjust/reduce the cell size if necessary. You can ignore the meshing for anti-pads and small shapes/voids through the Preferences settings.

Read on for more details …

Analyze Menu

All analysis functionality is available on the main PDN Analysis GUI:


 

In the mesh dialog, there is a brief description for meshing and all functions:


 

Preferences

Selecting the Preferences button brings up the Preferences form:


 

The General tab sets many of the default values. The Simulation tab sets the frequency range and maximum number of points for frequency-domain analysis, duration time, and time step for time-domain analysis. The top section of the Field Solver tab contains the settings for mesh generation:


 

The Mesh settings are one area of settings where a tradeoff between accuracy and performance is set. The default settings are for a Regular mesh with all voids in shapes included in the mesh. If you select the Ignore option from the following drop-down list, then all anti-pads of vias/pins will be ignored during the meshing. If you select the Include option, then all anti-pads of vias/pins will be meshed exactly:


 

You can ignore small island shapes or small voids by specifying a value for Ignore all shapes/voids less than:

    


This value is a scale factor of the maximum mesh cell size you specified (fine, regular or coarse or custom size).
Start the mesh by selecting the Mesh button on the Power/Ground Plane Meshing form:


 

Once the meshing is started, you will see a progress dialog appear and then the PDN Audit Results:

 


Mesh Results

Depending on your layer settings or specific design configuration, you may not see any mesh displayed in your design:



 
To aid in reviewing any PDN results including mesh generation, it is recommended that you pin the Options and Visibility fold out window panes in the PCB SI canvas:


 

The Options panel displays the type of analysis run and allows you to cross probe to the canvas and select the layer to review. Use the Review pull-down in the Options panel to review a specific layer of interest in the design. Select the mesh in the canvas to see the net name appear in the Options panel:


 

Please share your experiences using this new 16.5 capability.

Jerry "GenPart" Grzenia

You are subscribed to email updates from Cadence PCB Design Blogs
To stop receiving these emails, you may unsubscribe now.
Email delivery powered by Google
Google Inc., 20 West Kinzie, Chicago IL USA 60610
mxbit.co.in/hw

Force-Sense Kelvin Connection

Cadence PCB Design Blogs

Cadence PCB Design Blogs



Customer Support Recommended – Appnote on Implementing the Force-Sense Kelvin Connection

Posted: 23 Aug 2012 07:01 AM PDT

The use of separate force (F) and sense (S) connections (often referred to as a Kelvin connection) is a common requirement in the PCB design. The separate force (F) and sense (S) connection at the load eliminates any errors resulting from voltage drops in the force lead. The Kelvin Sense connection is routed by separating the sensing signals (S) from the lines, and delivering the power to the load (F). This type of connection prevents noise related problems in a closed loop system because it allows for more accurate measurement of the sense voltage at the load.

Consider the following figure:

A long resistive PCB trace is still used to drive the input of a high resolution Analog-Digital Converter (ADC), with low input impedance. In this case, however, the voltage drop in the signal lead does not give rise to an error, as feedback is taken directly from the input pin of the ADC and returned to the driving source. This scheme allows full accuracy to be achieved in the signal presented to the ADC, despite any voltage drop across the signal trace.

The requirement is to implement this at the schematic created using Allegro Design Entry HDL (DEHDL) to drive the PCB board created using Allegro PCB Editor so that both Force and Sense signals can be identified and constrained independently, and still allowed to be physically shorted in layout.

Flow Overview

This flow is based on a special logical symbol, which is created and saved in a library. The force sense library symbol(s) has shorting schemes defined within the symbol definition, which allows the engineer to seamlessly define the nets to be force sense. When placed in a schematic, the shorting scheme will short at least two sense lines to a force line. While packaging the schematic, separate nets are generated for the Sense and Force lines which are passed on to the PCB board file. As shown in the image below, four sense lines are connected to a force line using the library symbol. Inside PCB Editor, a symbol gets placed, and defines the location of the short for force and sense signals.

The pins of the schematic symbol will have a unique property called PIN_SHORT whose value consists of the logical pin names. While packaging the schematic (running File > Export Physical), based on the <project>.CPM directive, the Packager-XL(PXL) acknowledges the PIN_SHORT property value and creates a NET_SHORT property with the value containing the physical net names connected to the logical pin names.

When you look at the PCB Editor DRA symbol for the footprint, you will see that the pins with different pad stacks are placed at the same location.

 

 

Constraint Assignment

This flow allows for individual net constraints to be assigned and used in the front to back flow. As an example, Max Propagation Delay and trace width can be defined.

Refer the following AppNote for the detailed procedure used to implement the Force-Sense (Kelvin) connection using Allegro Design Entry HDL (DEHDL) & Allegro PCB Editor.

Click here for the AppNote.

Note: The above link can only be accessed by Cadence customers who have valid login credentials for Cadence Online Support (http://support.cadence.com).

Cadence Customer Support

You are subscribed to email updates from Cadence PCB Design Blogs
To stop receiving these emails, you may unsubscribe now.
Email delivery powered by Google
Google Inc., 20 West Kinzie, Chicago IL USA 60610
mxbit.co.in/hw

APD’s Wire Bond Settings

Cadence PCB Design Blogs

Cadence PCB Design Blogs



What's Good About APD's Wire Bond Settings Groups? You'll Need the 16.5 Release to See!

Posted: 21 Aug 2012 08:00 AM PDT

The 16.5 Allegro Package Design (APD) product has been modified to provide a different type of method to control wire bond settings for groups. It is important to note the differences between these new group settings and the wire bond groups that existed prior to 16.5. In these prior releases, a wire bond had to strictly adhere to a wire bond group, whereby the group defined the characteristics of the wire bond. In contrast, no group settings need to be tagged to wire bonds. They are optional and simply a means to quickly assign characteristics to a set of wire bonds without being attached to them. They are more extensible since the designer can define one or more attributes instead of a specific number of wire bond attributes. Also, they can be re-used from design to design.


Read on for more details …


This feature provides an alternative manner for setting up wire bonds in the design. If the designer wishes to use this capability, the recommendation is that they follow this flow:
1.     During design initialization, load the file of pre-defined wire bond settings groups.
2.     During wire bonding, select the settings group that applies to the fingers being added or modified. If items from multiple settings groups are being modified, do not select a settings group.
3.     If new settings groups are added or existing groups modified at the end of the design cycle, export these for use in future designs.

The most common use model here will be to load an existing set of settings groups from a pre-defined XML file. To do this, open the settings groups form and browse to the master definitions file. Alternatively, the designer will enter this form and manually define the settings groups. When finished, they will most likely save this out to disk for later reuse across similar designs.

When performing wire bonding, the designer can select a settings group from the pull-down list of defined groups to apply that group's configuration to the ministatus panel and, thus, any objects currently selected for manipulation.

Menu and Command-Line Access


This feature does not exist as a standalone command. It is available through the Route > Wire bond > Settings (or RMB > Settings if in a wire bond command already) command.  

The screenshot below illustrates the user interface for creating, importing, and exporting wire bond setting group definitions. This is available via a new button on the main Route > Wire bond > Settings form (see the second screenshot below):


 
•       Active Group: This is the group that is currently under edit in the "Definition" section lower in the form. Defaults to the first group alphabetically if there are groups defined for the current drawing.
•       Add: Press to add a new settings group definition.
•       Copy: Press to copy the current settings to create a new group definition based on it (will also require a group name, just like add).
•       Delete: Press to remove the active group definition from the database.
•       Master Definitions: This pull-down will allow the user to select from any standard group definition files found in their techpath (works the same as the wire profiles master definitions pull-down). Alternatively, the designer can select the "Browse…" entry to browse to any available file on disk, or the Clear option to disassociate with the master definitions file.
•       Save…: Save the set of group definitions from this database to an external XML formatted file for reuse in other designs.
•       Refresh from Master: Press this button to refresh the definition of the active from the master definitions file. Again, it works similarly to the profile definitions form button of the same name.
•       Checkboxes beside fields in the "Definition" area of the form: When one of these checkboxes is checked, that field will be configured when the active group is selected. If unselected, the existing value for this field will be left unchanged when this group is selected.
•       Value fields in the "Definition" area of the form: If the checkbox beside a field is enabled, then the value field will be configurable. The selectable / enterable values for the fields are exactly the same as those you would be able to select / enter for the corresponding field of the wire bond add, move, or change characteristics form. For example, the "Bubble" field has options of "Shove All", "Shove Path", and "Shove Off".

Here is a screenshot showing the new button for accessing the pre-defined wire bond group settings:


 

Finally, when you're in one of the wire bond adding / editing commands, such as changing characteristics, there is a new field in which you can select a pre-defined settings group to configure fields on the form. One illustration of the form is shown below for the Add Wire bond command. Whenever the Add Command is invoked, this field is blank. The designer can select any existing pre-defined group settings in the database. If a group is selected, the attributes of that group are reflected on the other fields on the form. For example - if group "JM_FING_GRP" defines an "Align with Wire" alignment, the current Alignment value with be changed to "Align with Wire":



 
As always, I look forward to your feeback!

Jerry "GenPart" Grzenia

You are subscribed to email updates from Cadence PCB Design Blogs
To stop receiving these emails, you may unsubscribe now.
Email delivery powered by Google
Google Inc., 20 West Kinzie, Chicago IL USA 6061
mxbit.co.in/hw

Allegro PCB Router Routing Changes

Cadence PCB Design Blogs

Cadence PCB Design Blogs



What's Good About Allegro PCB Router Routing Changes? 16.5 Has a Few New Enhancements!

Posted: 15 Aug 2012 08:00 AM PDT

The 16.5 Allegro PCB Router has a couple new improvements I'll cover today – Embedded Components Support and Route Quality Improvements.

Read on for more details …


Embedded Components Support

This functionality is basically transparent to the Allegro flow designer. The Router will just translate and route these components normally. For standalone users of the Allegro PCB Router, a new syntax has been added to support via keepouts that are required by embedded components for proper routing. For standalone users, changes have been made to add keepouts needed for embedded components.

Routing:

Proper fanouts should be completed before using the Router to ensure access to other layers. The fanouts for embedded components can go up or down as parts are no longer top/bottom mounted. If embedded devices are placed on plane layers, the router can't access pins on these layers. Also, the Allegro PCB Router can't terminate a via on a plane layer ,so fanout routines cannot do via-in-pad at these locations. So, the recommendation is to NOT place embedded components on plane layers.

Route Quality improvements

The Allegro PCB Router has focused on the quality of differential pair routing in particular.

Differential pair routing:

The routing engine has been enhanced to consider differential pair objects as a single entity and avoid the splitting of the differential pair. This will especially help when the differential pair is entering a regular pin array or BGA.

New Cost has been added to control the differential pair routing. This will allow designers to control the routing of differential pair when the differential pairs may split:

    cost dp_push_squeeze [free|forbidden|[0-100]]

[free]    Diffpair can be squeezed to produce uncouple violation (actual gap < gap-tolerance-) if required to produce DRC-free layout. actual gap < min_line_spacing is not allowed, and push is considered as failed.

[forbidden] Diffpair after push should maintain exact primary/neck gap; any squeeze is illegal.

However, Setting the value to forbidden may increase delay failures.

Post Routing Diff Pair Clean up improvements:

Enhancements have been made in post route geometry clean up for differential pairs. The improvements include, but are not limited to cleaning up staired patterns, removing bends, cleaning uncouple bumps and reliability improvements.
This further enhances the router's ability to provide good diff pair solutions. There are no additional controls or commands needed for these improvements. The "Clean" and "Critic" commands have been enhanced to incorporate these changes.

Please share your experiences using these new 16.5 capabilities.

Jerry "GenPart" Grzenia

You are subscribed to email updates from Cadence PCB Design Blogs
To stop receiving these emails, you may unsubscribe now.
Email delivery powered by Google
Google Inc., 20 West Kinzie, Chicago IL USA 60610
mxbit.co.in/hw

Allegro PCB Editor GUI

Cadence PCB Design Blogs

Cadence PCB Design Blogs



What's Good About Allegro PCB Editor GUI updates? See for Yourself in 16.5!

Posted: 07 Aug 2012 10:40 AM PDT

The 16.5 Allegro PCB Editor release contains several updates to the Graphical User Interface (GUI) to increase your efficiency and productivity in using the product.

Read on for more details...

Status Bar updates

Functional responses can be obtained by clicking fields in the status bar. For example, the field indicating the current subclass can be selected and changed to a new class/subclass. This is a good alternative to opening the Options Form over in the side panel.

Class / Subclass

In previous releases the subclass panel has reflected the active subclass of the design when the etch class is active, and has been blank in other situations. New in 16.5 is a hover prompt indicating "Active class and subclass - Click to select." Clicking on this field produces a popup that enables you to change the active class/subclass setting from a list. In addition, the field itself will list the subclass for all classes, as well as the class name when a non-etch class is active:




 

Application Mode


In previous releases, the application mode provided a read-only abbreviated indication of the currently active app mode (e.g. "GEN" for General edit). In 16.5, the full application mode is spelled out and the hover prompt shows "Application Mode is <App Mode Name>. Click to select". As with class/subclass, clicking on this field produces a selectable popup listing all available application modes. Subsequently selecting one of those will put Allegro into that application mode:




 
Super Filter

The text "Click to select" is appended to the hover prompt for this field, and clicking it will result in a selectable popup listing possible super filter values for you to assign:


 

Number of Selections

A new field at the far right of the status bar panel indicates how many objects are presently selected in the canvas, along with the prompt text "Number of selected objects." This is also be a selectable field, with a popup offering you the following options previously available only within the app mode RMB "Selection set" popup:

  • Clear all selections
  • Select by Polygon
  • (When multiple selections) Narrow select (has a pull-right to select object type for selection filtering)
  • Object browser. . . (brings up the Find by Name / Property dialog)
  • (When multiple selections) Select (has a pull-right to filter selection to an individual object)
  • (When multiple selections) Toggle select (has a pull-right to highlight individual objects without deselecting the others)



 

Polygon Select Done


The polygon select command has been enhanced to automatically finish on a double LMB click. This is similar to selecting "done."

Zoom Button in Pick Dialog

A "Zoom" button has been added to the "pick dialog" to allow application mode user access to the zoom center command:


 


As always, I appreciate your feedback on how you're using these new 16.5 capabilites in Allegro PCB Editor.

Jerry "GenPart" Grzenia

You are subscribed to email updates from Cadence PCB Design Blogs
To stop receiving these emails, you may unsubscribe now.
Email delivery powered by Google
Google Inc., 20 West Kinzie, Chicago IL USA 60610
mxbit.co.in/hw

Increase Performance in Allegro

Cadence PCB Design Blogs



Appnote Shows How to Increase Performance in Allegro PCB Editor

Posted: 16 Jul 2012 09:00 AM PDT

While working on very large scale Printed Circuit Board (PCB) files that contain a huge stack-up along with thousands of footprints and numerous shapes, the performance of the  Allegro PCB Editor plays an important role in getting the board built in time. Below are example statistics for a large scale PCB:

Apart from upgrading the platform hardware to have more RAM, multi-core processor, or abetter graphics adapter, there are several capabilities you can leverage in the Allegro PCB Editor that will help improve the overall performance.

Have you ever wondered how the Performance Advisor can improve the overall performance of Allegro PCB Editor when working on large board files?

 

 

 

Performance Advisor will analyze a design for possible performance issues and generate a report that provides solutions and recommendations to better manage your PCB design. It is an important check when working on large designs.The report generated would consist of objects responsible for performance degradation like constraints in the design that are not being used, constraint regions defined but with no values, or overlapping shapes.

To access Performance Advisor, select Tools > Database Check from the Allegro PCB Editor. This launches the DBDoctor utility. Performance Advisor is a new utility added in DBDoctor GUI and is available from SPB 16.3 release.

In SPB 16.2, you will need to select Setup > User Preferences > Early_adopter and then select Performance Advisor to enable this function within DBDoctor.

If you are working with large scale designs and/or would like to improve the overall performance of the tool, the following Application Note should be helpful. This Application Note will cover other areas which when tweaked appropriately will improve the overall performance of the PCB Designs in Allegro PCB Editor.

Please click here to access the Appnote

Note: The above Appnote can only be accessed by Cadence customers who have valid login credentials for Cadence Online Support (COS) .

The Cadence SPB Customer Support Team

 

 

 

You are subscribed to email updates from Cadence PCB Design Blogs
To stop receiving these emails, you may unsubscribe now.
Email delivery powered by Google
Google Inc., 20 West Kinzie, Chicago IL USA 60610
mxbit.co.in/hw