high-density interconnect

mxbit Cadence PCB Design Blogs What's Good About Allegro PCB Router HDI Capabilities? 16.5 Has a Few New Enhancements! Posted: 08 May 2012 11:51 AM PDT More high-density interconnect (HDI) improvements including the tuning of the auto-router (Allegro PCB Router - SPECCTRA) to use the via patterns, alignment of via list priority with Allegro PCB Editor, and creation and removal of anti-acid bars are available in the 16.5 release of the Allegro PCB Router. Read on for more details… In this release, the SPECCTRA auto-router provides the ability to use inset/tangency and stagger via patterns. Autorouting with Via Patterns The auto-router takes into consideration effective inset/tangency rules to find the most optimal 3D path. Usage of via patterns is regulated by via and via pattern costs. Ordered Via Lists In Allegro PCB Editor, the via lists were prioritized, but prior to the 16.5 release, the Allegro PCB Router did not have this capability. The 16.5 release now provides this ability. This command will turn on/off the prioritization of the via list provided by Allegro. set follow_usevia_priority on/off Note: It is best to set this switch to on ONLY when working with HDI structures. When using standard PCB structures it is preferred to NOT set this switch. Anti-acid bars To avoid the acid traps at tangent/inset bbvias/microvias, Allegro PCB Router allows the creation of anti acid bars. These are rectangular bars created on each layer to avoid the acid traps. The anti-acid bars are created by using the following command: create_anti_acid_bar This command may be used to remove the anti-acid bars remove_anti_acid_bars The Allegro PCB Router constructs an anti-acid bar for each pair of tangent/inset bbvias as a path on a shared layer with the valid width values: I welcome your feedback on these new 16.5 capabilities. Jerry "GenPart" Grzenia Free PCB Signal Integrity Education from Robert Hanson Continues at Cadence in Austin Posted: 08 May 2012 08:54 AM PDT Over fifty PCB enthusiasts ascended upon the Cadence campus in Austin, Texas last month where they were greeted by world renowned signal integrity educator Robert Hanson.  Robert spent two full days taking them from the basics of transmission line theory all the way through the challenging aspects of compliance of serial interface standards running at 8 gigabits per second.  And if that was not enough, he then went into an in-depth description of why power delivery network (PDN) analysis is required.  The room was packed with engineers getting a great two day education. After two days of classroom academics, the students then were offered a third day of free education which featured hands-on experience using Cadence Allegro signal and power integrity tools. In the morning of the third day, the students were able to run extensive signal integrity analysis on a DDR memory system as well as high speed serial links using IBIS-AMI models to drive the multi-gigabit interfaces.  In the afternoon, the students focused on using the Allegro PDN analysis technology which allows for power integrity checks directly from the design database without the need for translation. A number of students commented that Robert Hanson's teaching and experience included good background and valuable historical data.  They enjoyed his presentation style and interaction with students which resulted in a valuable two days of classroom education.  And the bonus of being able to take the classroom education into the lab and actually run the Cadence signal and power integrity tools made the experience even more valuable. If you were one of the lucky ones that were able to take advantage of this three day event, please give us your comments below.  If you are interested in learning more about Allegro PCB SI or PDN analysis tools, please click here. TeamAllegro You are subscribed to email updates from Cadence PCB Design Blogs To stop receiving these emails, you may unsubscribe now. Email delivery powered by Google Google Inc., 20 West Kinzie, Chicago IL USA 60610