ESD Risk

Cadence PCB Design Blogs Shocking Rules and Material Remove ESD Risk in Allegro PCB Smartphone Designs Posted: 27 Jun 2012 08:30 AM PDT Static electricity can send shocks through your body.  We have all experienced walking across carpet on a dry day and then touching a metal doorknob.  This shock discharge is formally known as Electrostatic Discharge (ESD).  ESD can be annoying to us on a dry day or when wearing nylon clothing, but it can be much more serious to electronic devices.  When the current associated with what may seem like a harmless shock enters into electronic equipment, the electronic components inside may suffer permanent damage. Working to resolve these ESD challenges is a privately held, San Jose based, venture backed company --- Shocking Technologies, Inc.  Its patented Voltage Switchable Dielectric™ (VSD) polymer nano‐composite material, XStatic®, can be applied to PCB and package substrates, and it dramatically improves ESD protection to the components in electronic devices.  When the material is combined with strategic PCB design rules, Shocking Technologies can boast that they provide the industry's only solution capable of up to 100 percent protection against ESD. While the electronics industry has recognized the need for ESD protection, the amount of protection provided by traditional methods only provides minimal protection.  Also, traditional methods risk adverse effects on high speed signaling interfaces making it difficult to meet compliance standards. And to make matters worse, with IC node geometry reductions, electronic components have become more susceptible to ESD due to the decrease in fabrication geometry size.  ESD engineering experts have recognized the need to better manage ESD, but also realized that an ESD solution cannot impact performance of the product.  And since handheld devices are the most susceptible to ESD, it is also recognized that an ESD solution must be cost sensitive in order to address the needs of the consumer market. The Shocking Technologies' VSD material is a polymer nano-composite that functions as an insulator (dielectric) during normal circuit operation and becomes conductive when the voltage increases beyond a predefined characteristic voltage. The VSD material becomes an insulator again after the voltage drops back below the characteristic voltage to normal operating levels.  The solution is of high value to any handheld product due to the susceptibility that comes with the day to day operation of such devices.   Shocking's XStatic™ material will clamp high voltage ESD events nearly instantaneously   Shocking Technologies and Cadence have agreed to collaborate together to provide automated support to their joint customers to enable up to 100 percent ESD protection.  Smartphone and tablet design teams under pressure to meet tight market windows will benefit from the automation that ensures predictable design cycles. Let us know about your thoughts about working with Shocking Technologies' XStatic material and Allegro PCB design tools. TeamAllegro This posting includes an audio/video/photo media file: Download Now You are subscribed to email updates from Cadence PCB Design Blogs To stop receiving these emails, you may unsubscribe now. Email delivery powered by Google Google Inc., 20 West Kinzie, Chicago IL USA 60610

ADW’s Bulk Editing

Cadence PCB Design Blogs What's Good About ADW's Bulk Editing? Check out the 16.5 Release and See! Posted: 18 Jun 2012 12:56 PM PDT The 16.5 Allegro Design Workbench (ADW) release provides bulk editing support. This is a huge time saver for librarians! The bulk editing provides you with the ability to operate on a set of parts or models. Read on for more details … In the ADW Library Workbench, when you Search by Classification, you can now:     Select multiple parts or models Edit-All Check-out Edit property values in list Add new part rows Edit linked properties (any linked model or property) JEDEC_TYPE PPLs EMBEDDED_PLACEMENT etc. Import /Export  CSV Check-in All Comments Apply to All option Release Verify/Release All Search by classification: Select parts from results list RMB – Edit All: Select Parts Node RMB – Check-out: Edits may be made on groups of models Edit comments, etc. To check-in the group of models, it is advised to turn off rules for simple edits, otherwise check-in individually Edit Field Values Ctrl/C copy Ctrl/V paste RMB menu items for easier and fast editing - Duplicate - Duplicates an existing row New Row – Adds new empty row Delete Row Export part data to a csv file, then import the csv to Excel, edit the data, then import the updated csv Edit/Add Associations Schematic models Footprint models Alternate Footprints Data sheets I look forward to your feedback! Jerry "GenPart" Grzenia You are subscribed to email updates from Cadence PCB Design Blogs To stop receiving these emails, you may unsubscribe now. Email delivery powered by Google Google Inc., 20 West Kinzie, Chicago IL USA 60610

Object Visibility Layers in DEHD

Cadence PCB Design Blogs What's Good About Object Visibility Layers in DEHDL? The Secret's in the 16.5 Release! Posted: 12 Jun 2012 02:00 PM PDT In the 16.5 Design Entry HDL (DEHDL) release, Object Visibility Layers are introduced. The different objects in DEHDL are now available on different layers and you are provided a toolbar for which the visibility of each of object layer can be controlled. This is similar to displaying layers of objects in Allegro PCB Editor. Read on for more details … The different DEHDL object types available are: Components/Symbols Nets Properties Notes Images The visibility of each object layer can be controlled by pressing or de-pressing the toolbar buttons. Pressing any object layer button makes that object invisible and de-pressing, shows the objects of that layer. On a schematic sheet, by default all the objects are visible and the toolbar looks like:   With this default setting, all the objects are visible on the schematic sheet:   By pressing any of the buttons, for example Nets, then all the nets are made invisible on the schematic canvas:     You can use the visibility toolbar to select objects of the same type to perform common operations. As an example, in the case of very dense schematics, this feature can be used to hide all the properties to make the connectivity of the design more clear.   The following steps explain the procedure of selecting objects:   1. Draw a selection box and everything inside gets selected. 2. Press all the visibility layer buttons one by one and see the objects of the particular layer disappear from the schematic canvas. 3. Press only the Symbols button and make all the symbols visible. 4. Select the menu option Group> Create> By Rectangle. 5. Draw a selection box and the symbols in the selection box become part of the group. 6. Select the menu option Group> Add Property… 7. Specify a property value pair: FOO = BAR 8. This property gets added to all the symbols which were members of the group. Please share your experience using this new capability. Jerry "GenPart" Grzenia You are subscribed to email updates from Cadence PCB Design Blogs To stop receiving these emails, you may unsubscribe now. Email delivery powered by Google Google Inc., 20 West Kinzie, Chicago IL USA 60610

APD's Wirebond Color Visibility

mxbit Cadence PCB Design Blogs What's Good About APD's Wirebond Color Visibility? You'll Need the 16.5 Release to See! Posted: 22 May 2012 11:51 AM PDT Prior to the 16.0 release, color and visibility (CV) settings of bond wires in Allegro Package Designer were based on the traditional layer model whereby wires were represented as 2-dimensional cline objects that could be colored and made visible or invisible depending on the layer they were on. In 16.0, bond wires were implemented as true 3-dimensional objects in the database, and their CV were set according to their profiles. The 16.5 release has made improvements to increase the designer's efficiency in setting the CV attributes. Read on for more details … Setting the wire profile visibility in Visibility tab With the new profile-based model, users are able to set the wire visibility in the Visibility tab. The following snapshots portray the Color form and the corresponding Visibility tab that lists wire profiles: The list of profiles starts after the last displayed layer. The profile list is the same as that in the Color form (i.e. the profiles in the database are listed in alphabetical order). If there are no profiles, nothing is listed after the layer list. The visibility tab is scrollable such that if there are a lot of profiles to be listed, they can all be accessed through the scroll bar. The workings of the check-boxes are the same as those for the layers - the result of setting or unsetting visibility is seen directly on the canvas. There is also a check-box at the top of the profile to quickly set or unset the visibility of all profiles. Eliminate WIRE subclass visibility setting Since 16.0, users have found indirect ways to affect the visibility of wires without going through the profile interface. In 16.5, we made the following changes in various areas of the tool: Hide the WIRE subclass check-box in the Color form and the Color command form so that users cannot directly manipulate the visibility of this subclass. Ensure that changes in WIRE subclass visibility from other applications get reflected to the profile visibility as well. Setting Wire DRC visibility in Visibility tab You can now set the visibility setting of the Wire DRC directly in the Visibility tab. This check-box is similar to the one in the Color Form: Being able to toggle this check-box in the Visibility tab allows for faster access to display or undisplay Wire DRCs in the canvas; toggling it OFF (background color) will undisplay all the Wire DRC markers (regardless of profiles), and toggling it ON (with the selected Wire DRC color) will show all those markers. I look forward to your comments. Jerry "GenPart" Grzenia You are subscribed to email updates from Cadence PCB Design Blogs To stop receiving these emails, you may unsubscribe now. Email delivery powered by Google Google Inc., 20 West Kinzie, Chicago IL USA 60610 http://mxbit.co.in

Allegro GRE 2 Point Flow

mxbit Cadence PCB Design Blogs What's Good About Allegro GRE 2 Point Flow? It's in the 16.5 Release! Posted: 15 May 2012 08:05 AM PDT The 16.5 Allegro Global Route Environment (GRE) has been enhanced by what we call a 2 Point Flow. These flows provide the benefit of both a guided flow and the simplicity of a default flow. The 2 Point Flow: Provides the benefits of a default flow - no path between the gather points Provides the guidance that is needed   - liberty to exit in the direction of choice For example, if you wish to provide 'no' guidance to some bundles, let the router pick the best path for all the members. So, you route the bundle spatially. Suppose you don't like the way the route exited the component. You wanted it to exit north instead of west as it chose to. Change the bundle's properties to be 'Guided', and place the gather points at the appropriate exit locations. Run the router again and you should see the routes exit the component in the desired direction, yet still be able to route on their own in between the gather points. Read on for more details  … In GRE, click the RMB on the bundle and select Bundle Properties > General: You can watch a video of this capability available on Cadence Online Support. Plan Spatial when Guide Router is OFF: Plan Spatial when Guide Router is ON: Please share your experiences using this capability. Jerry "GenPart" Grzenia You are subscribed to email updates from Cadence PCB Design Blogs To stop receiving these emails, you may unsubscribe now. Email delivery powered by Google Google Inc., 20 West Kinzie, Chicago IL USA 60610

high-density interconnect

mxbit Cadence PCB Design Blogs What's Good About Allegro PCB Router HDI Capabilities? 16.5 Has a Few New Enhancements! Posted: 08 May 2012 11:51 AM PDT More high-density interconnect (HDI) improvements including the tuning of the auto-router (Allegro PCB Router - SPECCTRA) to use the via patterns, alignment of via list priority with Allegro PCB Editor, and creation and removal of anti-acid bars are available in the 16.5 release of the Allegro PCB Router. Read on for more details… In this release, the SPECCTRA auto-router provides the ability to use inset/tangency and stagger via patterns. Autorouting with Via Patterns The auto-router takes into consideration effective inset/tangency rules to find the most optimal 3D path. Usage of via patterns is regulated by via and via pattern costs. Ordered Via Lists In Allegro PCB Editor, the via lists were prioritized, but prior to the 16.5 release, the Allegro PCB Router did not have this capability. The 16.5 release now provides this ability. This command will turn on/off the prioritization of the via list provided by Allegro. set follow_usevia_priority on/off Note: It is best to set this switch to on ONLY when working with HDI structures. When using standard PCB structures it is preferred to NOT set this switch. Anti-acid bars To avoid the acid traps at tangent/inset bbvias/microvias, Allegro PCB Router allows the creation of anti acid bars. These are rectangular bars created on each layer to avoid the acid traps. The anti-acid bars are created by using the following command: create_anti_acid_bar This command may be used to remove the anti-acid bars remove_anti_acid_bars The Allegro PCB Router constructs an anti-acid bar for each pair of tangent/inset bbvias as a path on a shared layer with the valid width values: I welcome your feedback on these new 16.5 capabilities. Jerry "GenPart" Grzenia Free PCB Signal Integrity Education from Robert Hanson Continues at Cadence in Austin Posted: 08 May 2012 08:54 AM PDT Over fifty PCB enthusiasts ascended upon the Cadence campus in Austin, Texas last month where they were greeted by world renowned signal integrity educator Robert Hanson.  Robert spent two full days taking them from the basics of transmission line theory all the way through the challenging aspects of compliance of serial interface standards running at 8 gigabits per second.  And if that was not enough, he then went into an in-depth description of why power delivery network (PDN) analysis is required.  The room was packed with engineers getting a great two day education. After two days of classroom academics, the students then were offered a third day of free education which featured hands-on experience using Cadence Allegro signal and power integrity tools. In the morning of the third day, the students were able to run extensive signal integrity analysis on a DDR memory system as well as high speed serial links using IBIS-AMI models to drive the multi-gigabit interfaces.  In the afternoon, the students focused on using the Allegro PDN analysis technology which allows for power integrity checks directly from the design database without the need for translation. A number of students commented that Robert Hanson's teaching and experience included good background and valuable historical data.  They enjoyed his presentation style and interaction with students which resulted in a valuable two days of classroom education.  And the bonus of being able to take the classroom education into the lab and actually run the Cadence signal and power integrity tools made the experience even more valuable. If you were one of the lucky ones that were able to take advantage of this three day event, please give us your comments below.  If you are interested in learning more about Allegro PCB SI or PDN analysis tools, please click here. TeamAllegro You are subscribed to email updates from Cadence PCB Design Blogs To stop receiving these emails, you may unsubscribe now. Email delivery powered by Google Google Inc., 20 West Kinzie, Chicago IL USA 60610

Via Pattern Support

mxbit Cadence PCB Design Blogs What's Good About Allegro Via Patterns During Group Routing? See for Yourself in 16.5! Posted: 30 Apr 2012 11:13 AM PDT New to the 16.5 release of Allegro PCB Editor is the ability to establish via patterns during group routing. Group Routing Review The Allegro PCB Editor supports interactive group routing. Interactive group routing is the routing of more than one net concurrently. You can use this feature when routing a bus with traces that follow the same path and have common physical and electrical rules. To specify the nets for group routing, select the elements (such as clines, pins, vias, and ratsnests) from which to route either by using the Temp Group option from the add connect pop-up menu, or selecting the elements with a window. Routing proceeds from the selected elements. Note: You can initiate a route by selecting ratsnest lines provided that you have enabled Ratsnests in the Find Filter. To reduce the incidence of accidental ratsnest selection, the editor ignores the ratsnests if you also select other types of elements. Note: If you are routing from a component with a complicated pin pattern, route from each pin to a location outside the component area. Then group the routes together (outside the component area) in the order that you want to route them as a group -- that is, organize the routes outside the component area so that the layout editor can order and space them properly. Read on for more details … Via Pattern Support Via pattern support during group routing is available when you are in the add connect command. You can add vias during group routing in both the modes-Alternate mode and Working layer mode. With the Alternate use-model enabled, you can select the via from the Options tab. With the Working Layer use-model enabled, you can pick the target-layer from the Add-Via dialog box. For adding vias in group routing, the same padstack (or via-stack) is used for all selected clines, and is determined by the control-trace. A DRC may appear if a padstack is invalid for one or more of the selected clines. Adding Via Patterns during Group Routing Select the add connect command using Route — Connect and create group to add vias. In the following figure four cline segments are selected. The control-trace is shown by the white X: Now select via-pattern from pop-up menu and add the via by double clicking the cline segments. The vias remain in the floating state until one additional click is made. New clines will gather, and then group route continues on the new layer. The via-pattern is created, and all the vias will slide dynamically as a group in the direction of the control-trace. The control-trace via is placed directly along the control-trace cline, with no extra vertices added. Extra vertices are added for the other traces if needed. Types of Via Patterns There are six type of via patterns. You can select the via pattern from pop-up menu. The Next Pattern option can be used to cycle to the next via pattern in the list: The shape of the via-pattern can change depending on which cline is the control-trace. To change the control-trace use the pop-up menu. Taper patterns produces the same result as one of the diagonal patterns if the control-trace is at the either of the end. If the vias are small, and/or the selected clines are already far enough apart, in group routing vias are added in-line, with no extra vertices. Adding Stacked Blind/Buried Vias During Group Routing For designs using stacked vias, you can select only those layers that can be reached with a single via-stack. The layers that can only be reached with staggered vias cannot be selected for adding vias in group routing. The example in the following figure shows three via-stacks (labeled "1-3"). You can add stacked vias during group routing by invoking the command once: If via-stacking is not allowed on layer three, then in order to add the vias from layers 3-to-6 you need to select add via second time, with layer six as the target layer. You can move vias labeled "3:6" vertically up or down until you click to drop them. To avoid any DRCs with the "1-3" via-stacks the "3:6" vias are placed in staggered form. Please share your experiences using this new 16.5 capability. Jerry "GenPart" Grzenia You are subscribed to email updates from Cadence PCB Design Blogs To stop receiving these emails, you may unsubscribe now. Email delivery powered by Google Google Inc., 20 West Kinzie, Chicago IL USA 60610