Tuesday, July 2, 2013

Cadence PCB Design Blogs



Cadence PCB Design Blogs

Cadence PCB Design Blogs


Posted: 13 May 2013 09:14 AM PDT
Just a brief blog today to introduce that 16.6 Allegro AMS Simulator (PSpice) now provides 64-bit data precision by default. This ensures a higher precision compared to the 32-bit data. For example, when a very small amplitude voltage is superimposed on a large voltage, the resulting voltage loses its resolution, displaying staircase waveforms. With 64-bit precision, for the same signal, a perfect ramp waveform is displayed.
Here's a simulation output with the 32-bit data precision set (notice the staircase style of output):
 
Now, change the Probe Data option to 64-bit:


Here's the resulting waveform (notice the smooth results):



I look forward to your feedback!
 
Jerry "GenPart" Grzenia

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Cadence PCB Design Blogs

Cadence PCB Design Blogs


Posted: 11 Jun 2013 07:46 AM PDT
The 16.6 Allegro PCB Editor and the Agilent Advanced Design System (ADS) interface have several new enhancements with respect to padstacks and vias.I will cover the Allegro generic via padstack that exports to ADS, and also the enhancements for existing layout IFF interface (import and export) to support the generic via exchange.
Layer-to-layer via structures are almost always used in PCB designs. These common structures are not standardized in ADS -- they are represented in several ways. These include instances of via models such as the microstrip VIA2 and as layout-only footprints that define the catch pads and drill holes with simple polygons.
The disconnection between the capabilities of PCB tool via structures, and the equivalent objects in ADS, makes design transfer difficult. A PCB tool via structure must be flattened to simple polygons for transfer to ADS, losing most of the information contained in the original PCB via. Likewise, those simple polygons can be transferred back to the PCB tool, but are not identified as a via structure and not treated as a layer-to-layer connection. ADS does not have the PCB compatible via library, which means there is no padstack definition for a generic PCB via.
To solve the problem, Cadence and Agilent developed a solution -- you can export Allegro generic via padstacks first from the PCB Editor, and then ADS will build a PCB-style via library with the pcbViaLib utility offered in ADS2011.10. Agilent has provided the pcbViaLib design kit, which provides via import utilities and a new ADS component, the pcbVia. This design kit defines a data file format that holds the definition of a PCB-tool style via structure, which is read by the pcbVia component and used with a layout macro to render exactly the same layout footprint in ADS as in the PCB tool.

When you export an Allegro layout design with generic vias to ADS by IFF, you can select export vias as components so all generic vias will be mapped to ADS via components. You can also use the via components in ADS layout and then export the ADS design with the kind of via components by IFF. When importing the design into PCB Editor by IFF, the I/F will automatically map back the ADS via components to Allegro generic via padstacks.

Here is the flow for via management between Allegro PCB Editor and ADS:

 


Read on for more details …

Export Allegro Generic Via Padstacks to ADS
There is a utility under the RF-PCB to export generic vias for ADS via component creation. You can click RF-PCB > Export Padstacks to ADS:


 
All vias used in the design will be listed and then you can select some/all vias to export. Please notice only vias in the layout will be listed on the form, so if you want to export a via padstack, you have to place the via into a design. The via group name is for ADS usage. Once you create the via components on the ADS side, you can place a via component in ADS layout from the specific via group.

Note: It's best to use a unique group name for each design so that ADS will not get confused. The exporting for via padstacks is not based on IFF format but AEL.

Constructing ADS Via Components
You can only get the required utility in ADS2011.10 or later. If you installed the specific design kit (you need to ask for it from Agilent), you will see this menu in ADS layout:





In ADS layout, click PCB Via Utilities > Import Via/Padstack Group… Browse to the proper .ael file exported from Allegro PCB Editor, then you will create the via components:

 
 
Export Allegro Design with Generic Vias to ADS by IFF
For a design with generic vias in PCB Editor like the following:

 
Click RF-PCB > IFF Interface > Export… to get the following dialog:

 
You can click the More options button, then you can see the Vias tab. Two options are available for via transfer mode. By default, all vias will be considered as components to export. You can still change it to Shape for the exporting as before. You can also RMB click on the header bar to select Change all to components as below:
 

If you export all vias as components, then all selected generic vias will be written out as via components in IFF file so that ADS can recognize them.

Import Layout IFF with Mapped Via Components into ADS
Make a new workspace in ADS and make sure the PCBVIALIB design kit is in current workspace. To import the design into ADS via IFF, click File > Import… in ADS layout, and then select the Cadence/PCB option, and browse the proper folder for the source files:

 

You will get the ADS layout will all generic vias converted into ADS via components:


 
If you double click a via in ADS layout, you will see the details for the via component:

 
Use Via Components in ADS
Once the via components created in ADS, you can export a layout design with generic vias from Allegro PCB Editor and then import the design into ADS by IFF. The Allegro generic vias can be replaced by ADS via components. Also you may directly use those via components in ADS side. Before you add a via component  into the design, you need to know which vias are available. You can click PCB Via Utilities > List Via Groups, all available via names and via groups will be listed:

 
To add a via component into ADS layout, you can directly enter pcbVia at the following field:

 
The following dialog will appear:

 
You may need to change the viaGroupName and viaName and also padTypes. You can get the viaGroupName and viaName by clicking PCB Via Utilities > List Via Groups. For padTypes, you need to manually specify the value.
The meaning of the padTypes is to specify the pad usage on each layer. On each layer there will be a figure (range: 0-7) to indicate the pad usage on the layer. For example, 2 means the pad on this layer is for anti-pad usage. 4 means the pad on this layer is used as regular pad.

The details of the definition for the padTypes are as following:

So when you use the via components in ADS, you need to know the layer number of the original via in Allegro design (when you export the padstack from Allegro).

Export Layout IFF with Via Components from ADS
Export a design from ADS layout by click File >Export…, and select the Cadence/PCB option form drop-down list:


 
Import IFF with Via Components into Allegro
In PCB Editor, click RF-PCB > IFF Interface > Import…, browse to the proper layout.iff file:

 
All via components in the IFF file will be mapped back to Allegro generic vias:

 


I look forward to your comments!

Jerry "GenPart" Grzenia

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Cadence PCB Design Blogs

Cadence PCB Design Blogs


Posted: 31 May 2013 09:30 AM PDT
Flexible PCBs are used widely in everyday technology and electronics in addition to high-end, complex completed components. Two of the most prominent examples of flexible circuit usage are in hard disk drives and desktop printers. The following blog highlights the features of Allegro PCB Editor (Allegro) along with the Miniaturization option that provides a routing solution for flexible (flex) circuits.
Flexible Circuit Technology
Flexible (flex) circuit technology is used for assembling electronic circuits by mounting the devices on flexible plastic substrates, such as polyimide or transparent conductive polyester film. As the name suggests, these circuits are flexible in nature and are used in consumer products as well as in computing applications and military equipment.
Some basic forms of flex circuits are:
  • Single layer - This construction entails circuits mounted on a single conductor layer made of metal or conductive polymer, over a flexible dielectric film.
      
  • Double layer - In this construction, flex circuits are placed on two conductor layers. Here, fabrication may require to be plated through holes, as needed.


     
  • Multi layer - The construction of flex circuits spanning three or more layers of conductors is known as a multilayer flex circuit. These multiple layers may not be continuously laminated together throughout the structure and may have openings, if needed.
      
  • Rigid flex - This structure is a combination of flex circuits placed on rigid as well as on flexible substrates. These are laminated together into a single structure.   
Board Outline
Flex boards are versatile in shapes. CAD design software, such as AutoCAD®, can be used to create a board outline that can be imported into Allegro PCB Editor. Allegro PCB Editor can import IDX, DXF, and IDF files that contain the outline, cutouts, and other mechanical features that are critical to the design.
                 
                                      CAD to BRD Translation 
Design Guidelines for Flex Circuits
Flexible-circuit designs not only face challenges similar to the ones rigid PCB designs face, but also some additional challenges. The very nature of a flex circuit is in its being able to bend and flex. This makes it as much as a mechanical device as an electrical one. This creates a special set of requirements unique to flexible circuitry.
Understanding how these requirements interact allows a PCB designer to create a flex circuit that balances the electrical and mechanical features into a reliable, cost-effective interconnect solution.
The guidelines used for designing flex circuits using Cadence Allegro PCB Editor are described in the subsequent sections.
Routing Consideration Using Route Keep Out
In general, users set up the cross-section for the maximum number of layers as per the design requirements.
Then a designer adds Route Keep Out areas as required for the cavity between Rigid and Flex or connectors. Included in the stack-up are many user-defined layers to represent the flex cover and masking layers. The designer may add a line or rectangle at the bend areas where traces are required to cross perpendicular.
                         Cover layers for rigid-flex design
An example layout requirement for a multilayer (6 layer) Rigid-Flex design -
        Example Layer Stack-up for rigid-flex design
Top and bottom layers are shield while inner layers are flex layers. There is a stiffener in the middle to strengthen the symmetry. The areas highlighted in red are cavities. It is recommended to place layer restricted Route Keep Out (RKO) in flex board areas to specify the cavity area and make a note for the fabricator on cavity requirements.
                               Route Keepout as Cavity
The designer can use the Z-copy command to copy the RKOs to the other layers where routing needs to be restricted. Placing a connector at the protruding flex Layer 2 or 5 can be controlled by editing the pads associated with the thru hole connector (Use the option of null in the Pad_Designer for the layers that are not relevant.)
Conductor Routing
Flex requires special considerations for routing due to its flexible nature and its versatility in shapes. Below are the routing capabilities from Allegro PCB Editor which can be employed for flex routing.
Multiline Routing
The flex-interconnect path generally spans across the flex section of Rigid-Flex design. The preparation entails testing multiple routes of specific widths and the respective conductor spacing as per the floor plan. Flex circuits mostly undergo potential reroute for the bus.
Using the Hug-Contour Option
Rigid-flex designs require curved bus lines. A flex board outline may also change during the design cycle. The ability to easily adjust the connect lines to the new form factor is critical.
The Multiline routing feature coupled with the hug-contour option lets the designer route multiple lines on the flex portion of the rigid- design in minutes instead of long hours based on traditional routing of one trace at a time.
              Example of multiline route abiding the route keepin as contour
New Slide Functionality for Arc Editing
With v16.6, a new slide functionality has been introduced. The slide command utilizes a move-intersect algorithm that delivers smoother and localized edits. This change simplifies the slide of the off-angle arc routing, and provides new options to improve efficiency. Note: The bubble mode is no longer allowed to wear down the arcs of an existing route.
Auto Interactive Convert Corner (AiCC) command
In v16.6, the Auto Interactive Convert Corner (AiCC) command has been introduced to improve efficiency in converting route corners in the Allegro design. You can interactively select nets, clines, or segments, for conversion to Arc, 45, or 90 degree corners.
Choose Route - Unsupported Prototypes - Auto Interactive Convert Corner.
AiCC can be run on existing Nets, Clines, or Segments
In v16.5, the glossing routine can be employed to convert 45- and 90-degree bends to arcs. It is useful for flex circuits because the resulting arcs may be time consuming to edit manually.
Refer to the AppNote for the detailed procedures on various routing methodologies discussed above, and also various other aspects that are not covered in the blog above.
Click here for the AppNote.
Note: The above link can only be accessed by Cadence customers who have valid login credentials for Cadence Online Support (http://support.cadence.com/).
 
Naveen Konchada
Cadence Customer Support
 

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Cadence PCB Design Blogs

Cadence PCB Design Blogs


Posted: 18 Jun 2013 01:15 AM PDT
Just a brief blog today about a new feature in Allegro PCB Editor.
A new net grouping mechanism has been added in Allegro PCB Editor 16.6 called 'NET_GROUPS'. Essentially, the Net Group replaces the bus object.
 A Net Group is a collection of net objects. Different types of net objects, such as nets, buses, differential pairs, and XNets can be added as members of a Net Group.  A net object can be a member of one Net Group only.

A Net Group can be constructed in the Constraint Manager.

If constraints are defined on a Net Group, the constraints are applicable to all members of the Net Group.  With the introduction of Net Groups, user-defined collections of net objects are now composed as a Net Group instead of a bus.

 

 

The Object Type for the Net Group is 'NGrp':

 

Please share your usage of Net Groups in Allegro PCB Editor.
 
Jerry "GenPart" Grzenia

Cadence PCB Design Blogs


Cadence PCB Design Blogs

Cadence PCB Design Blogs


Posted: 25 Jun 2013 10:11 AM PDT
The complexity of the designs is constantly increasing and more and more logic is being placed inside hierarchical blocks. This leads to an increase in the number of interfaces that are exposed by the hierarchical block. The increased number of interfaces means more pins are required on the block symbol. In many cases, the block symbols become so big (e.g. FPGAs, large pin count devices) that they cannot be placed on a  standard page border. These large block symbols also become difficult to manage because of the many pins coming out of the same symbol.

The 16.6 Allegro Design Entry HDL release provides a solution to better manage the hierarchical block symbols by splitting them into multiple split symbols. This has been an often requested enhancement! Instead of generating a big monolithic symbol, you have an option to split the ports of the hierarchical block over multiple symbols. This reduces the size of the block symbol. Also, the ports can be logically categorized and placed on different symbols to create symbols that can be placed across schematic sheets, especially near the circuitry to which they connect to. This makes placing the symbols much simpler and managing numerous pins easier.
This functionality is available in the 16.62 release.

Read on for more details …

The Allegro Design Entry HDL (DEHDL) Component Browser now shows a hierarchical block's split symbol viewing and instantiation:

 

Schematic operations include -
–    The symbol version can be changed using the RMB Menu
–    Cut / Copy / Paste / Delete
–    Moving of split symbols across pages
–    Ascend / Descend Split Symbols
–    Highlight  / Cross Probing


 

There are several Hierarchy Viewer Operations:
–    Display a single entry for each block instance
–    Display a block identifier name (SPLIT_BLOCK_NAME)
–    Selection opened the first page of the block schematic instance
–    RMB Menus
     –    All operations are the same
     –    Select instance lists all split block instance symbols
     –    Selecting an entry navigates to the selected block split symbol


 


To generate a split symbol hierarchical block, you use Genview. There's a new option to generate split symbols:


 

The distribution of pins across symbols can be done by using the Distribute Pins dialog or via Auto Distribution:


 

 

The Distribute Pins Dialog allows you to –
  • Select one of more ports and move them to a symbol
  • Contains buttons for main commands
  • Provides sorting and filtering
  • Has an option to Retain Graphics for each symbol
  • Ensure a port exists only on one symbol
  • Utilize RMB Menu commands
 

 

 

You also have the ability to use the command line genviewHDL command as well as importing via a text (.csv) file.


I look forward to your feedback on experiencing this new capability!

Jerry "GenPart" Grzenia