Tuesday, July 2, 2013

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Posted: 25 Mar 2013 09:55 AM PDT
In the Allegro PCB SI 16.6 release, vias in SigXp have been enhanced to make it more efficient for design use. In addition, Allegro PCB Editor padstacks will be used to build the models.
Read on for more details …


Adding Vias

Adding a via is easier and faster than before. You no longer have to go through the Via Model Generator to create a model nor are you required to search the list of existing models that fit the need. The difference is that you are now adding a via rather than a via model. The via may not be pre-solved to a specific model.

The current way of adding a via in SigXp is still supported and unchanged. You can still add a via model on the canvas.

In order to add these "dynamic" vias in SigXp, a layerstack will have to be present in the topology. In a new topology this can be accomplished by using the Manage LayerStacks function to create or import a layerstack. When a topology is extracted from Allegro, the layerstack of that board is automatically imported in the topology.

A new via is added with two nodes (two connection points) on the canvas. When newly added, the two nodes are not tied to any specific layer as they will take on the properties of the connected node, so the label of those nodes will be Layer1 and Layer2:


 
If a trace is connected and is on a particular layer then the via node is assumed to be on that layer and will take its properties. In the case of a "floating trace" (a trace not on a layer stack layer), the via node will take its properties and still say LayerX (unchanged). Since we do not know what layer that is, we will assume the top or bottom most layer of the via structure:


 
The prior release (16.5) via toolbar button is a two-part button which lists all available via models on the right hand side pulldown:


 
Clicking on the left side of the button (the one with the via image) brings up the Add Element Browser. In 16.6, the left part of the Add Via button will add the new "dynamic" via with only two nodes. The pulldown remains unchanged to list the pre-solved via models.
Reuse of Via Models
You will want to reuse already solved via models in SigXp. To do that, the same technique used today is available. You can either select the right button of the Add Via toolbar button, which will list all existing via models available sorted by types, or RMB > Add Element can still be used to choose the desired via model.
When these via models are added to the canvas, the model is "locked" to the via and cannot be changed - this is the via model that will be used to simulate.
Via Parameters
The new (dynamic) via has the following parameters which are listed in the standard parameters spreadsheet. These parameters can be modified:

 
model    The via model associated with the via. A via which has no model yet will have UNMODELED as a model. Once solved, the name of the model will be used.
viaOutputFormat    The format with which the model was solved. If no model exists yet, the format is blank.
viaPadstack    The name of an available padstack. This parameter is a pulldown which lists the available padstack files on disk and in the library.
viaTopLayer    The top most layer of the via drill.
viaBottomLayer    The bottom most layer of the via drill.
For coupled vias the parameters will be a little different. It will show the via name with which it is coupled as well as the distance between them. Aside from that, it will look just like a single via.

Padstack Consumption
SigXp can now consume and optionally modify the same padstacks as Allegro PCB Editor. You can to import *.pad files and keep them as file if they are different than the library.

You can access the Via Padstack Manager through the menus using Setup > Manage Via Padstacks, or by right clicking in the SigXp canvas and selecting Manage Via Padstacks. Editing or creating a new padstack will use the same padstack editor available in Allegro. The padstack can be saved as an external file. If shapes are associated with the padstack, they will be stored in the same location. All information in the padstack relevant to the via is used to generate the model:


 

Via Modeling
When a new "dynamic" via is added to the topology, no model is associated with it. Only when you perform a simulation or manually solve the via will the field solver be called. In batch mode, the field solver uses the standard via modeling preferences that are currently found in PCB SI. These settings are available in SigXp and can be accessed through the menus using Analyze > Via Setup Preferences or by right clicking in the SigXp canvas and selecting Via Setup Preferences:


 
The via subckt section is built using the padstack information, the layerstack and the connected traces, as is done in Allegro PCB SI. The via model is stored in the working IML file.
Coupling Vias
With this feature, you can couple 2 single vias to form one single model. You can select 2 vias in the SigXp canvas and select Couple from the right mouse button menu:


 
When the Couple function is used, you will be required to specify a spacing between the vias:


 
This spacing is added to the parameters in the spreadsheet:


 
When you select a coupled via, all vias in the set will be selected:


 
You can decouple the vias by selecting Decouple from the right mouse button when one of the vias is selected:



Please share your experiences using these 16.6 features.
Jerry "GenPart" Grzenia

Cadence PCB Design Blogs



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Posted: 05 Nov 2012 10:33 AM PST
The Component Alignment feature is available in Placement Edit Application mode. It was introduced in the Allegro PCB Editor 16.3 release and now enhanced in 16.6 to support the following new options:
  • Alignment Edge
    • When aligning vertically, select 'left' or 'right' as the edge to base the alignment on
    • When aligning horizontally, select 'top' or 'bottom' as the edge to base alignment on
  • Spacing Options
    • Use DFA Constraints - Compress components in the selection set to their minimum DFA clearances.
    • Equal Spacing - Algorithm computes space between the first and last component of the selection set then divides by the number of components resulting in an equalized spacing gap between each component. Use the increment/decrement controls to adjust component spacing real time.
Read on for more details…

When you window-select a group of components you can hover over the anchor component and select RMB – Align Components. The Options Panel for Alignment controls include -
  • Alignment Direction – Horizontal or Vertical
  • Alignment Edge – Bottom, Center, Top or Left, Center, Right
  • Spacing – Off, DFA, Equal

 


Here's an example showing 'Alignment Edge' to 'Top'. The alignment is based on the place-bound shapes of each symbol:

 

Here's an example showing 'Use DFA constraints'. This effectively compresses the selection set to the Minimum DFA clearance rule between each of the components:

 


In the following example, we've done a window-select of 3 connectors, then selected RMB – Align Components -
  • Select the 'Equal spacing' – The computed space between each connector in this example is 123.50 mils.
  • Use the '+' option to increment the space (value of your choice)
  • Use the '-' to decrement the space

Here's an example showing that in the value field adjacent to the decrement and increment buttons, you can enter specific values (in this example - 25 mils). You can click on the '+' and '–' buttons  to decrement/increment the spacing gap by the specified value you entered:

I look forward to your feedback!

Jerry "GenPart" Grzenia

Cadence PCB Design Blogs



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Posted: 13 Nov 2012 06:00 AM PST
In some designsflows, you need to connect two plane shapes on the same net, but on different layers, together with vias in order to improve connectivity. These "shorting" vias are placed in a regular pattern across the overlapping areas of the shape, in such a way as not to interfere with any routing on layers between the two shapes.
The 16.6 Allegro Package Designer (APD) product now provides a mechanism for constructing these arrays of shape-to-shape shorting via arrays, deleting them, and updating them as the design progresses.

Read on for more details …

You first select the two shapes to be shorted together. This will update the form fields to restrict the padstacks available, and, if parameters already exist for this shape pairing, will optionally load the existing via array values. You can customize any fields as necessary on the form, and finally presses the "Add Vias" or "Remove Vias" button to perform the desired operation.
Note:  If the two selected shapes already have a via array between them, it will be cleared before generating a new array.
Manufacture > Shape Via Shorting:

 
The RMB popup menu, shown below, contains the standard Done, Oops, and Cancel items.
As well as entries for add vias and for remove vias:


 
 
  • Padstack: This will list only those via padstacks applicable for the currently selected shapes. For instance, when the command is first started (no shapes selected), it will show all via padstacks in the design. When you select the first shape, the list gets trimmed to just those that start or end on the specified layer. When the second shape is selected, it is fully restricted to only those padstacks going between those two specific layers. At any time, if the current selection becomes invalid for the selected shapes, the tool will change to the first padstack alphabetically.  
  • Spacing: The airgap between vias in the via array. This is derived from the current selected via padstack and pitch. You should ensure this value is at least equal to your via to via DRC constraint value for the constraint set this net belongs to.  This defaults to the via to via DRC spacing constraint on the top layer of the design.
  • Pitch: The center to center distance between vias in the shorting via array. This is tied to the spacing value above, and changing one will change the other.
  • Array Angle: The angle at which the array will be created. A 0-degree angle means all the vias are placed in horizontal rows / vertical columns like a standard grid. Adding an array angle is useful is the shape is primarily at an angle (think like the spokes of a wheel). The default value will be 0 degrees.
  • Rotate Vias at Array Angle: If you specify an angle for the array above, and the padstack definition consists of any non-circular pads, drill holes, etc., you may wish to have the vias instantiated with a rotation that matches the array angle to maintain consistent separation. This option allows you to do that.
  • Starting Position: Where the reference point for the via array is. Choices are upper left/right, lower left/right, and custom point. The corner selections are relative to the reference shape's extents box.
  • Offset X / Y: The offset X and Y values relative to the indicated starting position. For example, an X offset of 50um from the upper left corner will have a "legal" via array position 50 microns to the right of the top-left corner of the reference shape's extents box. The array will extend from this point in all directions, at the pitch and angle specified, to cover the entire shape region.
  • Custom Point X/Y: If the starting position is "Custom Point", these fields are enabled, and allow you to specify an absolute database position to use as the via array's reference position. This is particularly useful if one needs to offset via arrays between different layer pairings, or if multiple via arrays connect to a single plane shape.
  • Use DRC Constraint Values: If enabled, this will cause the tool to pull the required spacing constraints from the DRC constraint system for the database. Thus, different values can be had on each internal layer, on each shape's layer, and in constraint regions. Defaults to on.
  • Via to Shape Boundary: If not using the DRC system's constraint values, you may enter a value for the vias to clear the two shorted plane shapes' outlines. This defaults to the via to shape spacing on the top layer of the design if enabled.
  • Via to Conductor (Shape Layers): If not using the DRC system's constraint values, you may enter a value for the vias to clear other routing objects (pins, vias, clines, etc) on the same layers as the shapes being connected. This defaults to the via to cline spacing on the top layer of the design if enabled.
  • Via to Conductor (Internal Layers): If not using the DRC system's constraint values, you may enter a value for the vias to clear routing objects (pins, vias, clines, shapes, etc) on all routing layers BETWEEN the layers the shapes being connected are on. This defaults to the via to cline spacing on the top layer of the design if enabled.
  • Update Form Values from Saved Shape Pair Settings: This option defaults to on. When a shorting via array is created between two shapes, the tool will store the array's parameters in the database. When these two shapes are next selected (and this option is enabled), the stored parameters will be updated to the form. This will include the values for all fields from the padstack through to the via to conductor spacing settings.
  • Add Vias: Add shorting array of vias between the two selected shapes. If shorting vias between these shapes already exist, they will first be removed. This will prevent duplicate vias in the database.
  • Remove Vias: If only a single (reference) shape is selected, this will remove all shorting via arrays between this shape and any other shape. If two shapes are selected, this will remove only those vias that connect specifically between the two selected shapes.

Example

Below we have a substrate with GND planes on the Surface and Base layers that we would like to connect with seed vias:


 
 
We bring up the Shape Shorting Via Array tool and set it as needed. Select the two shapes to be shorted on the work surface and then select the Add Vias button:


 
 
The shapes are now shorted together per our settings:


 

Please share your experience using this new capability!
Jerry "GenPart" Grzenia

Cadence PCB Design Blogs



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Posted: 26 Feb 2013 09:47 AM PST
The Allegro AMS Simulator (analog/mixed-signal) 16.6 release adds several enhancements to the Advanced Options dialog form. This enables the customizability of a PSpice simulation run, including control over convergence homotopy options, making worst-case analysis independent of RELTOL and enabling auto-convergence automatically in case of convergence failure. These options do not change the core behavior of the simulator, but provide the designer new ways to control the behavior at different simulation points.
Options have been added to the Advanced Analysis Options dialog box in the following areas:
--Bias-Point Convergence
--Integration Method
--Voltage Limiting
--Worst-case Deviations
--Max-Time Step Control
--Pseudo Transient
--Relative Tolerance

Read on for more details…


Here are the new options available in the Advanced Analog Options form:

 


Convergence Improvement Options:
– Advanced Biaspoint Convergence Homotopies
– Integration method option
– Node Value Limiting
– Relative Tolerance

Accuracy Improvement Options:
– Worst-case control independent of RELTOL
– Behavioral sources TimeStep Control for sinusoidal functions
– MinStep independent of TSTOP
– 64-Bit Data accuracy
For the Biaspoint Convergence:
  • PSEUDOTRAN
    • Bias-point Convergence Enhancement
    • Used when all other methods (STEPGMIN, STEPSOURCES) have failed
  • ADVCONV
    • Enables all convergence algorithms, viz. PseudoTran, StepGmin, and StepSources (ON by default)
  • GMINSRC
    • Enables StepGmin from inside of StepSources
  • NOSTEPDEP
    • Suppresses stepping of dependent sources during StepSources
  • GMINSTEPS
    • Maximum number of steps per iteration of StepGmin
  • ITL6
    • Maximum number of steps per iteration of StepSources
  • PTRANSTEP
    • Maximum number of steps per iteration of PseudoTran

For the Transient Convergence:
  • METHOD = [TRAPEZOIDAL|GEAR|DEFAULT]
    • Integration method to be used during Transient analysis
    • Gear is more stable, so more often used in the default mode
    • Trapezoidal is more accurate
  • TRTOL
    • Tolerance for integration error calculated during transient analysis
    • A higher value implies more tolerance, so bigger time steps and reduced accuracy
    • Can be useful to jump model discontinuities in case of fastswitching designs
    • Default = 7
There are also new PSpice Options:
  • LIMIT
    • Absolute limit on data values calculated in PSpice engine during simulation
    • Can be used in case of overflow errors
    • Can also be useful for convergence failures in some simulations
  • WCDEVIATION
    • Deviation to be used for Worst-case analysis
      • Default calculation for worst-case Delta is nominalValue * RELTOL
      • If WCDEVIATION is specified, it gets modified to nominalValue * WCDEVIATION
  • PROBE64
    • 64-bit Probe data
    • Increases resolution of probe
    • Very useful for differential probes
  • NOGMINI
    • Suppress GMIN addition across current sources
    • Gives more accurate results for very low current values
  • BRKDEPSRC
    • Sets automatic break-points for sinusoidal behavioral sources
    • Useful for long simulations when default Max Time Step is too big

I look forward to your feedback!

Jerry "GenPart" Grzenia

Cadence PCB Design Blogs



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Posted: 04 Mar 2013 10:30 AM PST
The Allegro PCB Editor Place Replicate application now supports the processing of component reference designators. The work performed in customizing assembly text or silkscreen to the seed circuit can now be leveraged across the replicated modules.

Read on for more details…

In the image below there are two modules. The one on the left (U14, U15 and the associated capacitors) has the text moved to locations which were determined to be appropriate. The module on the right would need to be updated to reflect the same text placement:


 
Once you have customized the text locations, use the Place Replicate 'Refresh' application to update the second circuit. The steps are:
1.    Set the 'Super Filter' to 'Module'
2.    Hover over the seed circuit then RMB — Place replicate — Update. Select/unselect additional etch as needed.
3.    RMB — Done. This will launch the file browser UI in which you can select the module you would like to refresh. Selecting the module and performing a save will update the module on disk and update the module(s) in the design.
 
 
 
 
 
As always, I look forward to your comments about this new capability.

Jerry "GenPart" Grzenia
 

Cadence PCB Design Blogs


Cadence PCB Design Blogs

Cadence PCB Design Blogs


Posted: 25 Mar 2013 09:55 AM PDT
In the Allegro PCB SI 16.6 release, vias in SigXp have been enhanced to make it more efficient for design use. In addition, Allegro PCB Editor padstacks will be used to build the models.
Read on for more details …


Adding Vias

Adding a via is easier and faster than before. You no longer have to go through the Via Model Generator to create a model nor are you required to search the list of existing models that fit the need. The difference is that you are now adding a via rather than a via model. The via may not be pre-solved to a specific model.

The current way of adding a via in SigXp is still supported and unchanged. You can still add a via model on the canvas.

In order to add these "dynamic" vias in SigXp, a layerstack will have to be present in the topology. In a new topology this can be accomplished by using the Manage LayerStacks function to create or import a layerstack. When a topology is extracted from Allegro, the layerstack of that board is automatically imported in the topology.

A new via is added with two nodes (two connection points) on the canvas. When newly added, the two nodes are not tied to any specific layer as they will take on the properties of the connected node, so the label of those nodes will be Layer1 and Layer2:


 
If a trace is connected and is on a particular layer then the via node is assumed to be on that layer and will take its properties. In the case of a "floating trace" (a trace not on a layer stack layer), the via node will take its properties and still say LayerX (unchanged). Since we do not know what layer that is, we will assume the top or bottom most layer of the via structure:


 
The prior release (16.5) via toolbar button is a two-part button which lists all available via models on the right hand side pulldown:


 
Clicking on the left side of the button (the one with the via image) brings up the Add Element Browser. In 16.6, the left part of the Add Via button will add the new "dynamic" via with only two nodes. The pulldown remains unchanged to list the pre-solved via models.
Reuse of Via Models
You will want to reuse already solved via models in SigXp. To do that, the same technique used today is available. You can either select the right button of the Add Via toolbar button, which will list all existing via models available sorted by types, or RMB > Add Element can still be used to choose the desired via model.
When these via models are added to the canvas, the model is "locked" to the via and cannot be changed - this is the via model that will be used to simulate.
Via Parameters
The new (dynamic) via has the following parameters which are listed in the standard parameters spreadsheet. These parameters can be modified:

 
model    The via model associated with the via. A via which has no model yet will have UNMODELED as a model. Once solved, the name of the model will be used.
viaOutputFormat    The format with which the model was solved. If no model exists yet, the format is blank.
viaPadstack    The name of an available padstack. This parameter is a pulldown which lists the available padstack files on disk and in the library.
viaTopLayer    The top most layer of the via drill.
viaBottomLayer    The bottom most layer of the via drill.
For coupled vias the parameters will be a little different. It will show the via name with which it is coupled as well as the distance between them. Aside from that, it will look just like a single via.

Padstack Consumption
SigXp can now consume and optionally modify the same padstacks as Allegro PCB Editor. You can to import *.pad files and keep them as file if they are different than the library.

You can access the Via Padstack Manager through the menus using Setup > Manage Via Padstacks, or by right clicking in the SigXp canvas and selecting Manage Via Padstacks. Editing or creating a new padstack will use the same padstack editor available in Allegro. The padstack can be saved as an external file. If shapes are associated with the padstack, they will be stored in the same location. All information in the padstack relevant to the via is used to generate the model:


 

Via Modeling
When a new "dynamic" via is added to the topology, no model is associated with it. Only when you perform a simulation or manually solve the via will the field solver be called. In batch mode, the field solver uses the standard via modeling preferences that are currently found in PCB SI. These settings are available in SigXp and can be accessed through the menus using Analyze > Via Setup Preferences or by right clicking in the SigXp canvas and selecting Via Setup Preferences:


 
The via subckt section is built using the padstack information, the layerstack and the connected traces, as is done in Allegro PCB SI. The via model is stored in the working IML file.
Coupling Vias
With this feature, you can couple 2 single vias to form one single model. You can select 2 vias in the SigXp canvas and select Couple from the right mouse button menu:


 
When the Couple function is used, you will be required to specify a spacing between the vias:


 
This spacing is added to the parameters in the spreadsheet:


 
When you select a coupled via, all vias in the set will be selected:


 
You can decouple the vias by selecting Decouple from the right mouse button when one of the vias is selected:



Please share your experiences using these 16.6 features.
Jerry "GenPart" Grzenia