Friday, March 22, 2013

Cadence PCB Design Blogs: Regulation Loop Design Using Allegro AMS Simulator


Cadence PCB Design Blogs

Cadence PCB Design Blogs


Regulation Loop Design Using Allegro AMS Simulator (PSpice)

Posted: 20 Mar 2013 10:47 AM PDT

Feedback regulation loops are widely used by power electronic designers. It is one of the most important and sensitive parts of a power supply circuit. An incorrect feedback loop design may cause oscillations in the circuit, and also increase the output voltage drops. In order to achieve a stable and tight regulation in the output, it is important to have a correct feedback loop.

To test a feedback loop, generally engineers use trial and error methods with the hardware. This takes a lot of time and labor. Moreover, it is expensive because components and/or PCB boards can be damaged. AMS Simulator (also known as PSpice) can be used by designers to test their loop designs without using any physical hardware circuits, and in the process save a lot of time and cost that goes into fine-tuning the design.

You can get a copy of a sample regulation loop circuit created in PSpice along with the simulation results: 

To download the Database Click Here
To view the Datasheet Click Here

To demonstrate a regulation loop and compensator circuit, an example circuit is designed with the MAX8566 component and is available in the Cadence PSpice library.

There are two sections: Open loop design and closed loop design.

Open loop design

You can create an open loop design using the Cadence AMS Simulator (PSpice) tool. Using the component MAX8566 available in the Cadence PSpice library, and the datasheet for MAX8566, you can implement an open loop design as per the following figure:

In the open loop design there is no feedback. So the output will increase or decrease with the variation of input voltage. The output voltage is not controlled -- hence V(out) increases as the input voltage increases. The goal is to get a constant 1.9 Volts at the output with a variation of input from 2.3 Volts to 3.6 Volts.

The figure below shows the output voltage waveform when the input supply is at 2.3 Volts, and V(out) = 1.9 Volts

The figure below shows the output voltage waveform when the input supply is at 3.6 Volts, and V(out) = 2.94 Volts

So, the output voltage V(out) increases from 1.9V to 2.94V when the supply voltage increases from 2.3V to 3.6V.

Closed loop design
 

From the datasheet of MAX8566, Pin 2 is the error amplifier output and Pin 32 is the feedback input.
Pin 25, REFIN, has the reference voltage, which is compared with feedback voltage (FB) to control the pulse width.

From the output filter the corner frequency of the circuit can be calculated as follows:  

fcorner=1/(2*Π*√L1*C1)  
Since C1 = 33μF, L1 = 200μH, fcorner ~= 2.0 KHz  

The filter gives two poles at 2.0 KHz. These two poles produce a phase shift of 180° that makes the output oscillatory. Hence two zeros have to be introduced to cancel the complex poles at the corner frequency and another pole at the origin. This gives a single slope (-20dB/decade) crossing at the '0'dB axis, which makes the loop stable. The pole at origin also decides the bandwidth of the converter.

Following the above discussion compensator circuit should have Pole at ω = 0 Hz and Zero at ω = 2 KHz, 2 KHz

Considering all practical conditions, it is advised to choose the Zero location at 1/10th of the calculated value.

For this design, Zeros can be considered at 200Hz. If the transfer function of the following circuit is derived, you can see that there are two zeros at fz1 and fz2 with one pole at fp where

fz1 = 1/(2*Π*R37*C10)= 200Hz
fz2 = 1/(2*Π*R32*C3)=200Hz
fp = 0Hz

After doing all the above changes, the design is ready for closed loop simulation. If simulation is run, following results appear in the PSpice probe window.

The voltage at OUT is constant V(out) = 1.9 Volt.The user can vary the input supply from 2.3 Volt to 3.6 Volt. The output voltage will be constant at 1.9 Volt. There is no oscillation at output voltage and it is stable.

Refer to the complete AppNote for a detailed procedure about each of the steps involved in the process.

Note: The above link can only be accessed by Cadence customers who have valid login credentials for Cadence Online Support (http://support.cadence.com).

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Tuesday, March 5, 2013

Cadence PCB Design Blogs: Allegro PCB Editor Place Replicate

http://mxbit.org
Cadence PCB Design Blogs

Cadence PCB Design Blogs


What's Good About Allegro PCB Editor Place Replicate Text Support? Check Out 16.6!

Posted: 04 Mar 2013 10:30 AM PST

The Allegro PCB Editor Place Replicate application now supports the processing of component reference designators. The work performed in customizing assembly text or silkscreen to the seed circuit can now be leveraged across the replicated modules.

Read on for more details…


In the image below there are two modules. The one on the left (U14, U15 and the associated capacitors) has the text moved to locations which were determined to be appropriate. The module on the right would need to be updated to reflect the same text placement:



 
Once you have customized the text locations, use the Place Replicate 'Refresh' application to update the second circuit. The steps are:
1.    Set the 'Super Filter' to 'Module'
2.    Hover over the seed circuit then RMB — Place replicate — Update. Select/unselect additional etch as needed.
3.    RMB — Done. This will launch the file browser UI in which you can select the module you would like to refresh. Selecting the module and performing a save will update the module on disk and update the module(s) in the design.
 
 

 

 

 

As always, I look forward to your comments about this new capability.

Jerry "GenPart" Grzenia

 


Saturday, March 2, 2013

Allegro AMS Options: adence PCB Design Blogs

http://mxbit.in/hw
Cadence PCB Design Blogs



What's Good About Allegro AMS New Advanced Options? They're in the 16.6 Release!

Posted: 26 Feb 2013 09:47 AM PST

The Allegro AMS Simulator (analog/mixed-signal) 16.6 release adds several enhancements to the Advanced Options dialog form. This enables the customizability of a PSpice simulation run, including control over convergence homotopy options, making worst-case analysis independent of RELTOL and enabling auto-convergence automatically in case of convergence failure. These options do not change the core behavior of the simulator, but provide the designer new ways to control the behavior at different simulation points.

Options have been added to the Advanced Analysis Options dialog box in the following areas:
--Bias-Point Convergence
--Integration Method
--Voltage Limiting
--Worst-case Deviations
--Max-Time Step Control
--Pseudo Transient
--Relative Tolerance

Read on for more details…


Here are the new options available in the Advanced Analog Options form:


 


Convergence Improvement Options:
– Advanced Biaspoint Convergence Homotopies
– Integration method option
– Node Value Limiting
– Relative Tolerance

Accuracy Improvement Options:
– Worst-case control independent of RELTOL
– Behavioral sources TimeStep Control for sinusoidal functions
– MinStep independent of TSTOP
– 64-Bit Data accuracy

For the Biaspoint Convergence:

  • PSEUDOTRAN
    • Bias-point Convergence Enhancement
    • Used when all other methods (STEPGMIN, STEPSOURCES) have failed
  • ADVCONV
    • Enables all convergence algorithms, viz. PseudoTran, StepGmin, and StepSources (ON by default)
  • GMINSRC
    • Enables StepGmin from inside of StepSources
  • NOSTEPDEP
    • Suppresses stepping of dependent sources during StepSources
  • GMINSTEPS
    • Maximum number of steps per iteration of StepGmin
  • ITL6
    • Maximum number of steps per iteration of StepSources
  • PTRANSTEP
    • Maximum number of steps per iteration of PseudoTran


For the Transient Convergence:

  • METHOD = [TRAPEZOIDAL|GEAR|DEFAULT]
    • Integration method to be used during Transient analysis
    • Gear is more stable, so more often used in the default mode
    • Trapezoidal is more accurate
  • TRTOL
    • Tolerance for integration error calculated during transient analysis
    • A higher value implies more tolerance, so bigger time steps and reduced accuracy
    • Can be useful to jump model discontinuities in case of fastswitching designs
    • Default = 7

There are also new PSpice Options:

  • LIMIT
    • Absolute limit on data values calculated in PSpice engine during simulation
    • Can be used in case of overflow errors
    • Can also be useful for convergence failures in some simulations
  • WCDEVIATION
    • Deviation to be used for Worst-case analysis
      • Default calculation for worst-case Delta is nominalValue * RELTOL
      • If WCDEVIATION is specified, it gets modified to nominalValue * WCDEVIATION
  • PROBE64
    • 64-bit Probe data
    • Increases resolution of probe
    • Very useful for differential probes
  • NOGMINI
    • Suppress GMIN addition across current sources
    • Gives more accurate results for very low current values
  • BRKDEPSRC
    • Sets automatic break-points for sinusoidal behavioral sources
    • Useful for long simulations when default Max Time Step is too big


I look forward to your feedback!

Jerry "GenPart" Grzenia


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