Thursday, May 24, 2012

APD's Wirebond Color Visibility

mxbit
Cadence PCB Design Blogs



Posted: 22 May 2012 11:51 AM PDT
Prior to the 16.0 release, color and visibility (CV) settings of bond wires in Allegro Package Designer were based on the traditional layer model whereby wires were represented as 2-dimensional cline objects that could be colored and made visible or invisible depending on the layer they were on. In 16.0, bond wires were implemented as true 3-dimensional objects in the database, and their CV were set according to their profiles.

The 16.5 release has made improvements to increase the designer's efficiency in setting the CV attributes.

Read on for more details …

Setting the wire profile visibility in Visibility tab

With the new profile-based model, users are able to set the wire visibility in the Visibility tab. The following snapshots portray the Color form and the corresponding Visibility tab that lists wire profiles:







The list of profiles starts after the last displayed layer. The profile list is the same as that in the Color form (i.e. the profiles in the database are listed in alphabetical order). If there are no profiles, nothing is listed after the layer list. The visibility tab is scrollable such that if there are a lot of profiles to be listed, they can all be accessed through the scroll bar. The workings of the check-boxes are the same as those for the layers - the result of setting or unsetting visibility is seen directly on the canvas. There is also a check-box at the top of the profile to quickly set or unset the visibility of all profiles.

Eliminate WIRE subclass visibility setting

Since 16.0, users have found indirect ways to affect the visibility of wires without going through the profile interface. In 16.5, we made the following changes in various areas of the tool:
  • Hide the WIRE subclass check-box in the Color form and the Color command form so that users cannot directly manipulate the visibility of this subclass.
  • Ensure that changes in WIRE subclass visibility from other applications get reflected to the profile visibility as well.

Setting Wire DRC visibility in Visibility tab

You can now set the visibility setting of the Wire DRC directly in the Visibility tab. This check-box is similar to the one in the Color Form:




Being able to toggle this check-box in the Visibility tab allows for faster access to display or undisplay Wire DRCs in the canvas; toggling it OFF (background color) will undisplay all the Wire DRC markers (regardless of profiles), and toggling it ON (with the selected Wire DRC color) will show all those markers.
I look forward to your comments.
Jerry "GenPart" Grzenia
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Saturday, May 19, 2012

Allegro GRE 2 Point Flow

 mxbit
Cadence PCB Design Blogs



Posted: 15 May 2012 08:05 AM PDT
The 16.5 Allegro Global Route Environment (GRE) has been enhanced by what we call a 2 Point Flow. These flows provide the benefit of both a guided flow and the simplicity of a default flow.
The 2 Point Flow:
  • Provides the benefits of a default flow - no path between the gather points
  • Provides the guidance that is needed   - liberty to exit in the direction of choice
For example, if you wish to provide 'no' guidance to some bundles, let the router pick the best path for all the members. So, you route the bundle spatially. Suppose you don't like the way the route exited the component. You wanted it to exit north instead of west as it chose to. Change the bundle's properties to be 'Guided', and place the gather points at the appropriate exit locations. Run the router again and you should see the routes exit the component in the desired direction, yet still be able to route on their own in between the gather points.
Read on for more details  …
In GRE, click the RMB on the bundle and select Bundle Properties > General:




You can watch a video of this capability available on Cadence Online Support.


Plan Spatial when Guide Router is OFF:





Plan Spatial when Guide Router is ON:




Please share your experiences using this capability.
Jerry "GenPart" Grzenia
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Thursday, May 10, 2012

high-density interconnect

 mxbit
Cadence PCB Design Blogs



Posted: 08 May 2012 11:51 AM PDT
More high-density interconnect (HDI) improvements including the tuning of the auto-router (Allegro PCB Router - SPECCTRA) to use the via patterns, alignment of via list priority with Allegro PCB Editor, and creation and removal of anti-acid bars are available in the 16.5 release of the Allegro PCB Router.
Read on for more details…

In this release, the SPECCTRA auto-router provides the ability to use inset/tangency and stagger via patterns.
Autorouting with Via Patterns
The auto-router takes into consideration effective inset/tangency rules to find the most optimal 3D path. Usage of via patterns is regulated by via and via pattern costs.

Ordered Via Lists
In Allegro PCB Editor, the via lists were prioritized, but prior to the 16.5 release, the Allegro PCB Router did not have this capability. The 16.5 release now provides this ability.

This command will turn on/off the prioritization of the via list provided by Allegro.
set follow_usevia_priority on/off

Note: It is best to set this switch to on ONLY when working with HDI structures. When using standard PCB structures it is preferred to NOT set this switch.


Anti-acid bars

To avoid the acid traps at tangent/inset bbvias/microvias, Allegro PCB Router allows the creation of anti acid bars. These are rectangular bars created on each layer to avoid the acid traps.

The anti-acid bars are created by using the following command:
create_anti_acid_bar

This command may be used to remove the anti-acid bars
remove_anti_acid_bars


The Allegro PCB Router constructs an anti-acid bar for each pair of tangent/inset bbvias as a path on a shared layer with the valid width values:



I welcome your feedback on these new 16.5 capabilities.


Jerry "GenPart" Grzenia
Posted: 08 May 2012 08:54 AM PDT
Over fifty PCB enthusiasts ascended upon the Cadence campus in Austin, Texas last month where they were greeted by world renowned signal integrity educator Robert Hanson.  Robert spent two full days taking them from the basics of transmission line theory all the way through the challenging aspects of compliance of serial interface standards running at 8 gigabits per second.  And if that was not enough, he then went into an in-depth description of why power delivery network (PDN) analysis is required.  The room was packed with engineers getting a great two day education.

Robert Hanson teaching in Austin
After two days of classroom academics, the students then were offered a third day of free education which featured hands-on experience using Cadence Allegro signal and power integrity tools. In the morning of the third day, the students were able to run extensive signal integrity analysis on a DDR memory system as well as high speed serial links using IBIS-AMI models to drive the multi-gigabit interfaces.  In the afternoon, the students focused on using the Allegro PDN analysis technology which allows for power integrity checks directly from the design database without the need for translation.
SI / PI Students gaining hands-on experience
A number of students commented that Robert Hanson's teaching and experience included good background and valuable historical data.  They enjoyed his presentation style and interaction with students which resulted in a valuable two days of classroom education.  And the bonus of being able to take the classroom education into the lab and actually run the Cadence signal and power integrity tools made the experience even more valuable.
If you were one of the lucky ones that were able to take advantage of this three day event, please give us your comments below.  If you are interested in learning more about Allegro PCB SI or PDN analysis tools, please click here.

TeamAllegro
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Via Pattern Support

mxbit
Cadence PCB Design Blogs



Posted: 30 Apr 2012 11:13 AM PDT
New to the 16.5 release of Allegro PCB Editor is the ability to establish via patterns during group routing.
Group Routing Review
The Allegro PCB Editor supports interactive group routing. Interactive group routing is the routing of more than one net concurrently. You can use this feature when routing a bus with traces that follow the same path and have common physical and electrical rules. To specify the nets for group routing, select the elements (such as clines, pins, vias, and ratsnests) from which to route either by using the Temp Group option from the add connect pop-up menu, or selecting the elements with a window. Routing proceeds from the selected elements.

Note: You can initiate a route by selecting ratsnest lines provided that you have enabled Ratsnests in the Find Filter. To reduce the incidence of accidental ratsnest selection, the editor ignores the ratsnests if you also select other types of elements.
Note: If you are routing from a component with a complicated pin pattern, route from each pin to a location outside the component area. Then group the routes together (outside the component area) in the order that you want to route them as a group -- that is, organize the routes outside the component area so that the layout editor can order and space them properly.


Read on for more details …

Via Pattern Support
Via pattern support during group routing is available when you are in the add connect command. You can add vias during group routing in both the modes-Alternate mode and Working layer mode. With the Alternate use-model enabled, you can select the via from the Options tab. With the Working Layer use-model enabled, you can pick the target-layer from the Add-Via dialog box. For adding vias in group routing, the same padstack (or via-stack) is used for all selected clines, and is determined by the control-trace. A DRC may appear if a padstack is invalid for one or more of the selected clines.
Adding Via Patterns during Group Routing
Select the add connect command using Route — Connect and create group to add vias. In the following figure four cline segments are selected. The control-trace is shown by the white X:




Now select via-pattern from pop-up menu and add the via by double clicking the cline segments. The vias remain in the floating state until one additional click is made. New clines will gather, and then group route continues on the new layer. The via-pattern is created, and all the vias will slide dynamically as a group in the direction of the control-trace. The control-trace via is placed directly along the control-trace cline, with no extra vertices added. Extra vertices are added for the other traces if needed.
Types of Via Patterns
There are six type of via patterns. You can select the via pattern from pop-up menu. The Next Pattern option can be used to cycle to the next via pattern in the list:



The shape of the via-pattern can change depending on which cline is the control-trace. To change the control-trace use the pop-up menu. Taper patterns produces the same result as one of the diagonal patterns if the control-trace is at the either of the end. If the vias are small, and/or the selected clines are already far enough apart, in group routing vias are added in-line, with no extra vertices.
Adding Stacked Blind/Buried Vias During Group Routing
For designs using stacked vias, you can select only those layers that can be reached with a single via-stack. The layers that can only be reached with staggered vias cannot be selected for adding vias in group routing. The example in the following figure shows three via-stacks (labeled "1-3"). You can add stacked vias during group routing by invoking the command once:




If via-stacking is not allowed on layer three, then in order to add the vias from layers 3-to-6 you need to select add via second time, with layer six as the target layer. You can move vias labeled "3:6" vertically up or down until you click to drop them. To avoid any DRCs with the "1-3" via-stacks the "3:6" vias are placed in staggered form.
Please share your experiences using this new 16.5 capability.

Jerry "GenPart" Grzenia
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